2022-02-08 02:00 AM
Hi,
I'm building a project using Cube MX (LL drivers) for the STM32U575ZITxQ processor (has SMPS) and I would like to get the processor into LL_PWR_REGU_VOLTAGE_SCALE4. Setting the MSIS to 16MHz achieves this but when I add in the 4 bit SDMMC interface in Cube MX the auto generated code only sets the regulator voltage to LL_PWR_REGU_VOLTAGE_SCALE3. This results in higher power consumption.
I am aware of the clock limitations of the SDMMC vs AHB bus and have adjusted PLL1P (sources SDMMC clock) to 16 MHz.
If I manually change the code to set it to SCALE 4 every thing seems to work ok but I would rather not deviate from the auto generated Cube MX code. Is it possible to achieve voltage scale 4 with SDMMC?
Many thanks
Ben
Solved! Go to Solution.
2022-02-09 04:49 AM
Hello @BSmit.7 ,
Actually this is a normal behavior, Range 4 is not allowed when using PLLs, HSI48 not divided by 2 or MSKI/MSIS having 48 MHz.
SDMMC uses either PLL1P or CLK48 as a source clock. In this case, Range 4 can be selected, when SDMMC uses CLK48 and CLK48 Clock Mux is set to MSIK.
PS: Adjust the frequencies according to your application and please make sure to enable LSE as it is required by the MSIK to calibrate itself.
I Hope this helps :)
If your issue is solved, please close this post by clicking the "Select as Best" button. This will help other members of the community find this response more quickly :)
Sara.
2022-02-09 12:25 AM
Hello @BSmit.7 ,
Thanks for your feedback,
Could you please share your ioc file and specify the CubeMX version ?
Thanks,
Sara.
2022-02-09 01:10 AM
Hi Sara,
Thanks for looking into this; Cube MX version 6.4.0.
The attached ioc file has:
Generating the code as-is for the ioc file will put the processor into LL_PWR_REGU_VOLTAGE_SCALE4 - line 124 of main.c for me.
If you enable the SDMMC1 in 4 bit mode this changes to LL_PWR_REGU_VOLTAGE_SCALE3
Many thanks
Ben
2022-02-09 04:49 AM
Hello @BSmit.7 ,
Actually this is a normal behavior, Range 4 is not allowed when using PLLs, HSI48 not divided by 2 or MSKI/MSIS having 48 MHz.
SDMMC uses either PLL1P or CLK48 as a source clock. In this case, Range 4 can be selected, when SDMMC uses CLK48 and CLK48 Clock Mux is set to MSIK.
PS: Adjust the frequencies according to your application and please make sure to enable LSE as it is required by the MSIK to calibrate itself.
I Hope this helps :)
If your issue is solved, please close this post by clicking the "Select as Best" button. This will help other members of the community find this response more quickly :)
Sara.
2022-02-09 07:11 AM
Thanks Sara, that has sorted it!
Ben