[STM32L4R9I Discovery Kit]ADC+DMA problems.

[SLi.21]

I would like to construct an sampling system via using ADC+DMA method on STM32L4R9I official Discovery Board. I use STM32CubeMX to configure the peripherals and then compose the HAL code in Keil-MDK. The problem I met is ADC&DMA works well, but the sampling value from temperature sensor is 4095(always appears this value). How can I solve this problem?

The configurations of peripherals are as follows.

1. ADC1 only connects to Temperature Sensor Channel(detailed configurations are showed in figure1).

2.DMA is configured as follows

3.main code(only edited parts are displayed)

 /* USER CODE BEGIN 2 */
	HAL_ADCEx_Calibration_Start(&hadc1,ADC_SINGLE_ENDED);
	HAL_ADC_Start_DMA(&hadc1,(uint32_t*)&val,1);
  /* USER CODE END 2 */
 
  /* Infinite loop */
  /* USER CODE BEGIN WHILE */
  while (1)
  {
    /* USER CODE END WHILE */
 
    /* USER CODE BEGIN 3 */
	  int i=val;
	  data[0]=48+i/1000;
	  data[1]=48+(i%1000)/100;
	  data[2]=48+(i%100)/10;
	  data[3]=48+i%10;
	  data[4]=0x0d;
	  data[5]=0x0a;
	  HAL_UART_Transmit(&huart3,data,6,1000);
	  HAL_ADC_Start(&hadc1);
	  HAL_Delay(20);
  }
  /* USER CODE END 3 */

[Ghofrane GSOURI]

Hello @SLi.21​ 

First let me thank you for posting .

Let's try this solution concerning the sampling time

The sampling time of an ADC is typically specified in ADC clock cycles, and it determines the amount of time that the ADC spends sampling the input signal before converting it to a digital value. The ADC clock frequency determines the maximum conversion rate of the ADC, and it is usually a good idea to choose a sampling time that allows the ADC to properly sample the input signal without introducing too much error or noise.

To calculate the sampling time in ADC clock cycles, you can use the following formula:

Sampling time (in ADC clock cycles) = (Sampling time (in seconds) x ADC clock frequency (in Hz))

For example: if you want to set the sampling time to 5 microseconds (5 x 10^-6 seconds) and the ADC clock frequency is 10 MHz (10 x 10^6 Hz), the sampling time in ADC clock cycles would be:

Sampling time (in ADC clock cycles) = (5 x 10^-6 seconds) x (10 x 10^6 Hz) = 50 ADC clock cycles

Please try this and I'll be waiting for your feedback.

Thx

Ghofrane