2024-06-10 05:41 PM
Hi,
I create a new project with STM32CubeIde 1.15.1 (but same with 1.10.1)
I add SDRAM 1 - BANK 1
When I debug this project, after HAL_SDRAM_Init function in MX_FMC_Init(), I can wath the memory in MEMORY BROWSER at address 0x60000000.
But on reference manual, SDRAM should be at 0xC0000000.
I select Default mapping in Bank Mapping :
If I select bank swapped, I have my datas at 0xC0000000.
Is it a bug of STM32CubeIDE ?
Solved! Go to Solution.
2024-06-18 03:52 PM
Isn't 0x60000000 the NOR FLASH on the STM32H743I-EVAL board?
What about after it's finished SDRAM_Initialization_Sequence() ??
or
2024-06-12 04:47 AM
Hello @COSEBE ,
Thank you for bringing this issue to our attention.
I reported internally.
The internal ticket 184015 (not accessible by community users) has been opened to confirm and fix the issue.
Thank you for your contribution in STCommunity.
Kaouthar
To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.
2024-06-12 07:07 AM
Hi Kaouthar,
Did you manage to reproduce the problem?
Is it a known problem?
Should I continu to investigate the problem?
2024-06-12 07:29 AM
Hi @COSEBE ,
I reproduced the problem and I reported internally to our STM32CubeMx team for confirmation and fix.
Also, I checked FMC_SDRAM example and it works correctly. For that, I recommend you to start with this example.
I think that SDRAM Initialization sequence shared in this FAQ How to set up the FMC peripheral to interface with... - STMicroelectronics Community can help you.
I will come back to you for more details as soon as possible.
Thank you.
Kaouthar
To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.
2024-06-12 09:00 AM
Honestly I think this problem is compounded because the Hardware has 0 / 1 signal designations, and then you refer to SDRAM Bank 1 and Bank 2, and the SDRAM chip itself has it's own understanding of "banks", with BA0 / BA1
ie
SDNE0 / SDCKE0 -> SDRAM1 aka BANK 1 -> 0xC0000000
SDNE1 / SDCKE1 -> SDRAM2 aka BANK 2 -> 0xD0000000
Given how systemic this has become, going to hard to rationalize it now..
2024-06-12 09:04 AM
Well, if that, It should be on every STM32H7, but it woks with STM32H7B3.
If that, I should have wrong address 0xC0000000 / 0xD0000000 but not 0xC0000000 / 0x60000000
2024-06-12 09:21 AM
Well this gets into another set of issues where the H7 family has at least 3 different die and they all behave differently, have different speeds and peripherals and occasionally have incompatible AF Mux settings.
H74x/H75x
H72x/H73x
H7Ax/H7Bx
2024-06-18 02:50 PM
This example is on bank 2.
Do you have a example on any STM32H7 working with SDRAM on bank 1 ?
2024-06-18 03:20 PM
Most of the H7 DISCO/EVAL BSP indicate use of BANK2, but the world is full of examples if you search, and the implementation is pretty orthogonal..
2024-06-18 03:21 PM
Can you check the example on repository H7 1.11.2 on STM32H743 ?
It is on bank 2 but still showing memory on 0x60000000 in my side