STM32G474RE ADC Clocking

[Jbin0101]

Hiya! 

I'm trying to figure out the clock config for my micro. I'm using ADC3 IN1 currently, and using the internal HSI clock source. Using the default settings, I can't seem to get anything better than 3.3 MSPS, and this is with a 10-Bit ADC resolution. From what I read, I should be able to get around 4 to 5 MSPS!

However, that's assuming the ADC is clocked at 60 MHz. By defualt, the ADC clock is divided by 4, so the resulting clock is at 42.5 MHz. Okay! So, I just need to change the divider ratio/or clock it to the PLLP to fix this.

However, I can't figure out a good way to get the prescaler to be okay with an async clock mode with a divider less than 4.

I've tried changing the PLLP clock divider ratio down to 6, which gives the ADC a clock of 56.666667. Won't let me change the prescaler still, stuck at async divide by 4.

Tried a PLLP clock divider of 5, which gives 68 MHz. Still can't change it to lower than 4. 

And changing the PLLP clock DOES impact my performance; I can change my trigger timer value and see my maximum sample speed change. If I manually change this line of code,

hadc3.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV4;

to lower divider values, it works as expected, and I get the higher sampling rates I want.

Why is CubeMX throwing a fit about this?

Using STM32CubeIDE 1.14.0. STM32G474-DPOW board.

[TDK]

Hover over the grayed out selection to understand the error.

In this case, it looks like CubeMX is using SYSCLK to determine this constraint regardless of the setting of the ADC345 clock mux.

[Jbin0101]

Is this intentional? I'm not sure if I'm just misunderstanding how clocking the ADC works or if this is a bug. :thinking_face:

[TDK]

No, it's almost certainly a bug. Perhaps @Semer CHERNI or @Amel NASRI can confirm or investigate.

[Semer CHERNI]

Hello @Jbin0101 

First let me thank you for posting.

After investigating the situation, I found that @TDK  is right about the fact that CubeMX is using the SYSCLK.

The issue is now raised internally for further analysis (170481: this is an internal ticket reference)

In the mean while you can change the divider value manually in the generated code to suite your need.

KR,
Semer.

[dpvileta]

Hello @Semer CHERNI and company; any updates with this? 

The issue was first reported in January, it is now last day of July. I have the latest version of CubeIDE (1.16.0) and the built-in MX will not allow me to change ADC345 Clock Mux. This looks like the same bug that @Jbin0101 had.

Is there an ETA for when this will be patched?

ADC345 Clock Mux cannot be changed

[TDK]

This is not the same issue as the OP.

To change the ADC345 mux, you first need to enable one of those ADCs. If that doesn't work, open up a new thread with relevant information and attach the IOC file.

[dpvileta]

@TDK Copy that - so has internal ticket reference # 170481 received any updates that can be shared, or has the ticket been closed/resolved?

Regarding the issue I mentioned, yes, I have had ADC3, ADC4, and ADC5 active in my project. So I will open another thread as you suggested.