I2C speed problems

[JonConesa]

Hi everyone,

I’m currently working on an I2C communication setup using the Nucleo-H753ZI DK but the cubeMx document is for the STM32H743BIT (the MCU for my custom board) and aiming to run it in Fast Mode (400 kHz). However, when configuring the I2C clock speed to 400 kHz, the CLK signal becomes unstable, as shown in the attached image.

To ensure the setup is functioning correctly, I ran tests with I2C configured at 100 kHz, and the communication works perfectly in that case.

I’ve also included an image of the system clock configuration in case there’s something that could be optimized.

Does anyone know what might be causing the instability in the CLK signal, preventing proper communication at 400 kHz?

Thanks in advance for your help!

[Andrew Neil]

What pullup value are you using?

Look at the signal on an oscilloscope to see what's happening:

https://electronics.stackexchange.com/a/473799

[TDK]

Increase the logic analyzer sample rate. Looks like it's just too slow to capture things at the resolution you're expecting. Compare sample rate to time between edges. Probably you only have 1-2 samples per pulse here.

[JonConesa]

Thanks a lot for your response!

Regarding the pull-up, I am using the MCU’s internal pull-up.

As for the logic analyzer, I’m using a Saleae Logic 8 with a 10 MS/s sampling rate.

Also, just to add, I’m working with the PCA555, which supports 400 kHz.

[TDK]

Include the .SAL capture file with the waveforms you show above here.

[padawan · Accepted solution]

Hi,

the internal pullups are to weak.(about 10k and more).

A good choice are 3k3 as pullup on the SDA and SCL lines.

hth

Padawan

[Ozone]

> Regarding the pull-up, I am using the MCU’s internal pull-up.

As mentioned, those are inappropriate.
Use a value between 10k and 1kOhm, more specifically 2k to 4kOhm.
The higher the speed, the lower go with the pull-up. These pull-ups form a RC low-pass element with stray and parasitc capacitances. Higher currents allow for a fast charge/discharge, and thus higher bandwidth.

> As for the logic analyzer, I’m using a Saleae Logic 8 with a 10 MS/s sampling rate.

You cannot assess signal quality with a logic analyser, which have fixed L/H thresholds.
You need a scope for that.

Logic analysers are (only) good for recording and decoding digital signals.

[Andrew Neil]

As the others have said, MCU (not just SMT32) internal pullups are too weak - especially when you're going for high speed!

Don't just guess at the pullup value; use an oscilloscope to pick  something appropriate - as shown earlier.

[JonConesa]

Hi Padawan, thanks for your reply!

It seems that the 3.3kΩ resistor resolved the CLK integrity issue. However, I’ve encountered a new problem regarding the CLK speed of the I2C. I’m aiming for a 400 kHz CLK speed, but currently, I’m getting a 378 kHz waveform instead.

The CLK speed is a critical parameter since the IC needs to operate at maximum speed. To achieve that I had to reduce the resistor to 100 Ohm. 

Thanks in advance!

[padawan]

Hi Jon,

How do you measure the frequency?

As andrew has noted use a scope.

The lower R has nothing to do with the clk.
The clk is generated by the Cpu and its clockdivder.

And the PCA can only pull 3mA down.

What vcc do you use?

5V? then you are limited to 1666 ohms. 3V-> 1k

padawan

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