2021-09-07 03:02 AM
In former CubeMX versions an Clock to ADC of 400MHz was possible
Now I am working on CubeMX V 6.3.0 with STM32Cube FW_H7 V1.9.0.
The maximum Clock frequency I can adjust is now 79MHz (selected clock source is the PLL2)
What is the meaning of the "79 to ADC (MHz)" exactly.
If, it is the input for the prescaler of the ADC, why it is limited to 79MHz
Wenn > 79 MHz is selected, CubeMX shows an error.
If it is the maximum Clock frequency of the ADC, why is it not limited to 50Mhz as discribed in the datasheet for the V design
V-design is also selected
Solved! Go to Solution.
2021-09-09 05:59 AM
Happy for that :smiling_face_with_smiling_eyes:
In this case, please click on the Select as Best button on my reply . This will help other members of the community find the answer more quickly .
Khouloud.
2021-09-07 03:34 AM
> STM32H7 CPU
Which chip exactly?
2021-09-07 03:51 AM
Sorry, STM32H743VG
2021-09-07 03:57 AM
With 75 MHz Clock selection, also an DIV1 is allowed, is there an addition divisior in between ?
Or an Bug in the CubeMX ?
2021-09-07 04:07 AM
It's likely just a bug in CubeMX. They have thousands of chips, hard to get everything right. I wouldn't go past the 50 MHz listed limitation. In any case, the max clock used in thier app note is 50 MHz.
CubeMX limits it to 80 MHz for me.
> With 75 MHz Clock selection, also an DIV1 is allowed, is there an addition divisior in between ?
Why would DIV1 not be allowed? The clock scheme is shown in the reference manual well.
2021-09-08 05:42 AM
Hello @Volker Bremauer, @TDK ,
First let me thank you for your feedbacks.
Actually, I assume that what you are observing is the expected behavior of STM32CubeMX.
To explain briefly the cause behind the displayed warning message in clock tree "ADC Clock Source frequency must be =< 80Mhz":
In fact, the frequency value you are seeing in the clock tree (which shouldn't exceed here the 80MHz in your case) is the adc_ker_ck, please refer to STM32H743xI/G Reference Manual > Table 59. Kernel clock distribution overview:
Thus, assuming that you're setting your Power Regulator Voltage Scale to VOS0, STM32CubeMX tool is correctly displaying the constraint of the maximum allowed adc_ker_ck.
Then, after dividing this value by the ADC prescalers we should not exceed the 50MHz/ 25MHz/ 12.5MHz/ 6.25MHz which are the ADC internal frequency as mentioned in the STM32H743xI/G Data Sheet > Table 184. ADC characteristics:
Hope this answers your question.
Please do not hesitate to raise any feedback/ issue.
Khouloud.
2021-09-08 09:19 AM
Thank you Khouloud for your detailed explanation.
One more Question:
How are the BOOST-bits set. In the older FW Version the was the possibility in the ADC_init structure.
hadc1.Init.BoostMode = ENABLE;
Thanks in advance
Volker
2021-09-09 03:23 AM
Hello @Volker Bremauer ,
Actually starting from the Firmware version STM32Cube_FW_H7_V1.4.0, the filed BoostMode is removed from ADC_InitTypeDef structure. Hence, the boost mode parameter is set automatically using a firmware function ADC_ConfigureBoostMode(ADC_HandleTypeDef* hadc); and it is no longer configurable through STM32CubeMX interface.
Boost configuration is handled by ADC driver inside HAL_ADC_Init there is a call to ADC_ConfigureBoostMode (in stm32h7xx_hal_adc.h file). This was done to avoid errors when setting these bits.
Hope that I've answered your question.
Khouloud.
2021-09-09 05:27 AM
Thanks a lot, now it´s clear for me, now I found the Boost setting in the firmware.
Best regards Volker:grinning_face:
2021-09-09 05:59 AM
Happy for that :smiling_face_with_smiling_eyes:
In this case, please click on the Select as Best button on my reply . This will help other members of the community find the answer more quickly .
Khouloud.