Processor: STM32F103
Using the SFR view in STM32CubeIDE, address 0x40006c00 is used for Register DR1;
looking into the software implementation this is actually 4 bytes before the DR1 register, resulting in a shift of DRx register by one.
Also according RM0008 the first 4 bytes based on above offset are reserved.
RN0114 (release notes for STM32CubeIde) are not mentioning this topic.
Implementation with HAL (for DR1 value 1 is handed as BackupRegister, resulting in an offset of 4 Bytes) :
uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
{
uint32_t backupregister = 0U;
uint32_t pvalue = 0U;
/* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
/* Check the parameters */
assert_param(IS_RTC_BKP(BackupRegister));
backupregister = (uint32_t)BKP_BASE;
backupregister += (BackupRegister * 4U);
