What's wrong with FMC seventh family

[Kondratev.Georgiy]

LCDHi all. I can’t figure out how to work in LCD interface mode. I check it with an analyzer and see that when writing a byte, instead of one FMC_NWE pulse, several are generated.

[Tesla DeLorean]

Caching, MMU, width of lines vs width of memory?

[Kondratev.Georgiy]

If I understand you correctly, the data format in the function and in the FMC node itself must match. If FMC is 16 bit then

#define TFT_DATA     *(__IO uint16_t*) 0x60020000

This happened with the F7 series, but not so with the H7...

[FBL]

Hi @Kondratev.Georgiy 

Could you explain please the behavior? You mean when writing a byte to LCD, multiple write cycles are being generated?

First, you can check the configuration of the memory ComSpaceTiming and AttSpaceTiming  Also, check the specifications MEMWAIT MEMSET and MEMHOLD...

[waclawek.jan]

You need to have the given area set as Device in MMU.

JW

[Kondratev.Georgiy]

Should this be done in the CORTEX M7 section? But I have difficulties with this, I do not understand this part of the kernel well.

[Kondratev.Georgiy]

Well, how would it work out. Described the region in CORTEX M7 with full access

created a definition by defining the address on line A16 (R/S signal)

 

#define ADDR_CMD    *(uint16_t*) 0x60000000
#define ADDR_DATA   *(uint16_t*) 0x60020000

and received the correct control signals for the TFT indicator at the output