2022-04-19 11:42 PM
Hello,
It's not clear for me what a peripheral reset (registers RCC_xxxRSTR) is doing. I didn't find the details in the reference manual. I assume it resets the internal state machine of the periph, its FIFOs, but for example does it also reset its configuration registers ? Is it described somewhere ?
regards
2022-04-20 12:43 AM
Good question.
> does it also reset its configuration registers?
From experience, yes.
> Is it described somewhere ?
Not that I know of.
JW
PS. An additional question would be, is it asynchronous, i.e. is it enough to toggle it for whatever short time, regardless of the peripheral's core clock setting and whether it's enabled at all.
@Imen DAHMEN , can you please have a look at this?
2022-04-20 03:59 AM
Hello @Gpeti , @Community member ,
It is same implementation as all STM32. The RSTR registers allows to reset the peripherals. It will control the reset signal of the peripheral.
The reset is asynchronous, it will resets the peripheral as soon as the bit is set high.
You need to take care when reset peripherals for example on AXI, if you reset the master/slave during an access it can result in system hang (protocol violation).
So, it is recommended to generate the reset when the bus is idle.
Hope that I've answered your question. If this the case, please close this post by clicking the Select as Best button. This will help other members of the community find that answer faster. :)
Imen
2022-04-20 04:40 AM
Thank you for your answer. However you don't explain exactly what the reset is doing in the peripheral. I assume it resets all registers, FIFOs and state machine to "defaut after product reset" state ? or is there a difference with for example POR ?
2022-04-20 05:02 AM
Sorry, I missed the point of reset the peripheral: interface registers, state machines etc… like a pin reset.
2022-04-20 06:50 AM
Hi Imen,
Thanks for your prompt reply.
I would suggest to put these pieces of information to the Reset subsection of RCC section. I don't think any of them is self-evident.
Thanks,
Jan
@Imen DAHMEN