STM32H5 GPIO toggling performance

[Brussl]

I use STM32H562 and/or STM32H503 (nucleo board). When try in loop only this line:

while (1)

{

GPIOB->ODR ^= GPIO_PIN_6;  

}

The frequency on pin is only 12.5 mhz. I use external quartz 8mhz (and 24mhz on nucleo)

I config  to 250mhz (with build-in CubeMX ) :

void SystemClock_Config(void)

{

RCC_OscInitTypeDef RCC_OscInitStruct = {0};

RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};

/** Configure the main internal regulator output voltage

*/

__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);

while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}

/** Initializes the RCC Oscillators according to the specified parameters

* in the RCC_OscInitTypeDef structure.

*/

RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;

RCC_OscInitStruct.HSEState = RCC_HSE_ON;

RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;

RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_HSE;

RCC_OscInitStruct.PLL.PLLM = 2;

RCC_OscInitStruct.PLL.PLLN = 125;

RCC_OscInitStruct.PLL.PLLP = 2;

RCC_OscInitStruct.PLL.PLLQ = 2;

RCC_OscInitStruct.PLL.PLLR = 2;

RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_3;

RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE;

RCC_OscInitStruct.PLL.PLLFRACN = 0;

if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)

{

Error_Handler();

}

/** Initializes the CPU, AHB and APB buses clocks

*/

RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK

|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2

|RCC_CLOCKTYPE_PCLK3;

RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;

RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;

RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;

RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;

RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;

if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)

{

Error_Handler();

}

}

Why is output frequency is too low ?. In assembler are no more 5 lines. So must be arround 50mhz.

[AScha.3]

and you set speed for mco hi ?

[Brussl]

Yes i have set " very high" speed. I see other interestig: if i choice source to MCO1 to be HSE or CSI , on MCO1 pin have a signal. And signal is exacly frequency according source , BUT if i choice PLL1QCLK - NOT SIGNAL.:

[AScha.3]

btw

set the pll1 fractional divider :0

[Brussl]

I set it 0 or other value , no mater. Just check and you will see that if you select for source PLL1Q - not signal !! Just test it. I see you dont trust me. JUST TEST !

[AScha.3]

Seems you dont believe me....

as i said: i tested this first, to proove , i set clk correct.

>>>

<<<

try same setting (100M -> mco/10) - otherwise i have no idea, why it shouldnt work on your H563.

[Brussl]

Do you have a kit with quarz as source not external generator ?

[AScha.3]

Its just original H563-nucleo board ; (un-modified...)

clk (8MHz) coming from st-linkV3 -> HSE bypass setting.

[Brussl]

"try same setting (100M -> mco/10) - otherwise i have no idea, why it shouldnt work on your H563."  - I check on H503 and H562.

Which is you version of HAL?

[AScha.3]

again ??

IDE v 1.13.1

[AScha.3]

+ check, what Cube puzzling together in SystemClk_config:

  /** Initializes the CPU, AHB and APB buses clocks
  */
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
                              |RCC_CLOCKTYPE_PCLK3;
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
  RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;

  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
  {
    Error_Handler();
  }
  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_PLL1Q, RCC_MCODIV_10);
}