Simulate a quadrature encoder on STM32F446RE

[Swyftfeet]

Noob here.  Using HAL and as much generated code as possible.   Ive run into an issue on how to self learn,  I've identified what I believe is the solution but nowhere( that I can figure out) in the reference document does it point to this in what I believe would be obviously described.

I have a situation where I am in need of using an MCU to simulate a quadrature encoder and some other inputs to a larger system for testing.  

The encoder goes from rest to 132kHz and back to rest 13 times a second. 

My first attempt was to use PWM/DMA and phase shifting but it kinda fell apart on me maintaining the phase shifts. 

I watched some videos and it occured to me that I could DMA a cyclic buffer through the GPIO without trying to maintain phase shift by writing directly to the GPIO: 

uint32_t enc_cycle[4];

for(int i=0; i<4 ;i++)

enc_cycle[i]=0;



enc_cycle[0] = 0x00000001;

enc_cycle[1] = 0x00000002;

enc_cycle[2] = 0x00010000;

enc_cycle[3] = 0x00020000;


HAL_DMA_Start(&hdma_tim1_up, (uint32_t)enc_cycle, (uint32_t)&(GPIOC->BSRR), 4);

HAL_TIM_Base_Start(&htim1);

HAL_TIM_OC_Start(&htim1, TIM_CHANNEL_1);

TIM1->DIER |= (1<<8);

After setting up the clock and Tim1 this works ok .  Using CubeMX and and DMA settings for circular word size buffer and TIM1_UP or TIM1_OC.  I get what I want from that timer as far as the 90deg phase shifted output.  Great!  

Changing the the 1's to 8's where applicable, it also works for Tim8 after going through the DMA setup in CubeMX.  Woot!

It does not work for any of the other timers in the same way.   GPIO stays dead when I follow the same setups on timers other than 1 or 8.   I dont know what key words I am missing.

Q1. My main question is how using the documentation would this be obvious? 

Pt 2.   I need to no modify the ARR of TIM1.  I was again going to attempt to use DMA  I was trying to use another timer (TIM4) as a slave Via ITR0 to TIM1 with a prescale of 4.      Again using the same DMA setup as above with the TIM4_UP and the code below:

uint32_t tim_cycle[20] = {5000,4000,3000,2000,1000,500,200,100,50,50,50,50,100,200,500,1000,2000,3000,4000,60000};

HAL_DMA_Start(&hdma_tim4_up, (uint32_t)tim_cycle, (uint32_t)& TIM1->ARR, 20);

HAL_TIM_Base_Start(&htim4);

HAL_TIM_OC_Start(&htim4, TIM_CHANNEL_1);

TIM4->DIER |= (1<<8);

Nothing happens to the ARR on TIM1

but if I change the the 4s to 1s it works fine!

Q2.   Again using the reference, how would I know this without experimentation, what is it that I am missing in the reference doc?

[SofLit]

Hello @Swyftfeet,

In next time please use </> button to paste your code. As per the current situation we cannot differentiate between the text and the code. I'm editing your post then.

PS: please review our recommendations on posting a thread in this community: https://community.st.com/t5/community-guidelines/how-to-write-your-question-to-maximize-your-chances-to-find-a/ta-p/575228

Thank you for your understanding.

[Swyftfeet]

Thank you, I also made a mistake in some of the code, line 18 in P1 should be &hdma_timer1_up

[SofLit]

fixed

[waclawek.jan · Accepted solution]

The answer to both questions is essentially the same: there is no connection from DMA1 to GPIO, nor to peripherals on APB2.

JW

[Swyftfeet]

Thank you, that website is treasure trove of useful information...

Trying to backtrack the correct answer you've given through the DataSheet and the Reference manual.  The fact that GPIO and APB2 peripherals only being addressable by DMA2 is non-obvious (to me) which is a shame.   

[waclawek.jan]

> The fact that GPIO and APB2 peripherals only being addressable by DMA2 is non-obvious (to me)

No, it's not obvious at all.

AN4031 mentions the DMA1 limitation to APB1 peripherals at its peripheral port in 2.2.1Dual DMA port but even that is easy to overlook,

Maybe some general introductory material to how systems-on-chip like STM32 are assembled and how do they work, would give a broader perspective especially to the first "system/memory" chapters of RMs and subsequently that would make issues like these easier to spot/explain. But I know of no such.

JW