Poor ADC quality on some Nucelo boards

[KubaPy]

Hi everyone :)
I need your help. I am currently writing my masther thesis and I need robust and not noisy ADC read. I am using Nucleo board in my project so I hope hardware should have no effect in my case. The problem is ADC quality. I've tested three different boards: F411RE(100MHz) F207ZG(120MHz) H745ZI-Q(400MHz). All boards were running with their internal RC clocks.

ADC for each one was configured in similar way i.e.:
- ADC clock around 7.5MHz,
- 12bit resolution,
- measurement frequency 10kHz (triggered from timer ISR),

- sample time around 15 cycles,

- polling method.

For test purpose I chose 1.5V battery to be measured and I realised that unfortunately only F411 returns stable voltage. I mean the noise was Vpp=10mV. Whereas the other mentioned boards delivered really unstable values (noise Vpp=250mV). I don't understand what is going on :frowning_face: 

Here is the code I've used for ADC measurement:

/* USER CODE BEGIN 0 */
#define ADC_RESOLUTION		4096
#define ADC_REF_MV			3300
#define SIGNAL_SIZE			1000U
volatile static uint32_t raw_signal[SIGNAL_SIZE];
volatile static int32_t signal[SIGNAL_SIZE];
static uint16_t idx = 0U;

void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
	if (htim == &htim4)
	{
		HAL_ADC_Start(&hadc1);
		HAL_ADC_PollForConversion(&hadc1, HAL_MAX_DELAY);

		raw_signal[idx] = HAL_ADC_GetValue(&hadc1);
		signal[idx] = (int32_t)raw_signal[idx] * ADC_REF_MV / ADC_RESOLUTION;

		if (++idx >= SIGNAL_SIZE)
		{
			idx = 0U;
		}
	}
}

/* USER CODE END 0 */

 If you happen to know any reason for my problem, please let me know in comments :frowning_face:

[David Littell]

Just a guess, is there a calibration step that should be done as part of the ADC initialization?

[KubaPy]

Imported by CubeIDE libraries for F411RE and F207ZG don't provide any calibration functions. Library for H745ZI does for both offset and linearity error correction, but I've already used them with no result.

[STOne-32]

Dear @KubaPy ,

Our Nucleos Boards are not the best for ADC accuracy in terms of PCB design and also separation of Digital and analog traces, due to low cost in purpose Kit . Regarding STM32F2 you can refer to this Application Note where we explain similar measurements done thru histogram method and how to make averaging .

https://www.st.com/resource/en/application_note/an4073-how-to-improve-adc-accuracy-when-using-stm32f2xx-and-stm32f4xx-microcontrollers-stmicroelectronics.pdf

Now, regarding the board and package which is LQFP144, F411 should be LQFP64 - you need to isolate Ground noise from digital on VSSA/VREF- pins when available and using a separate low noise power for VDDA/VREF+ as shown in this application note 

https://www.st.com/resource/en/application_note/an2834-how-to-optimize-the-adc-accuracy-in-the-stm32-mcus-stmicroelectronics.pdf

Hope it helps you .

Ciao

ST1

[KubaPy · Accepted solution]

SOLUTION

Luckily I've found this post:
https://community.st.com/t5/stm32-mcus-products/fluctuations-in-adc-value-of-stm32h743-mcu/td-p/331487/page/2

The author of the solution said that Ethernet PHY causes the ADC noise problem and recommended to remove L2 coil which turn off this interface. I did so and below there are results before and after:

Standard deviation of measurement dropped hugely from near 90 to 1,5.

It seems to be problem with every H7 Nucleo board as each has PHY. The conclusion is that there is no way to use both Ethernet and ADCs, since ADC averaging/oversampling isn't possible in every situation.

[gregstm]

Sounds like you have cut down the noise greatly. In general, if I had to do precise ADC measurements with a nucleo board, I would create a separate daughter board with its own very low noise linear voltage regulator and amplifier to buffer the signal before it got to the nucleo board. To take it one step further, I would have a separate ADC chip on that daughter board and just communicate with it via SPI. I would use plenty of surface mount ferrite beads to block high frequency noise (and plenty of capacitors too)