How to reset counter value ?

[FAJOL.1]

This post was originally attached to this old, solved thread:

https://community.st.com/t5/stm32-mcus-products/how-to-reset-counter-value/td-p/175202 

Hi,

in my case this technique has some drowback. It seems that using the macro  __HAL_TIM_SET_COUNTER 

to reset cause interrupt request. I mean..

I m using too the F401RE and I configured the TIM5 with Input Capture on channel 1 and Output Compare on channel 2. I need to reset the counter since overflow would cause some errors on my code (I have to measure the delays between rising and falling edges). Output Compare function is used to stop the acquisition..

I tries the macro to reset the counter, or even setting the UG bit in the  TIMx_EGR register.  I tried also to play with 

URS and UDIS as reported here:

How to reset STM32 timer? - Stack Overflow

and in the in the reference Manual RM0368 (check in the Attachements).

I really don't undestand  if UDIS have to be = 0 or 1 if I want to restart the timer without any interrupt to arise.

Here my code.  

void resettaCounter(TIM_HandleTypeDef *htim, uint32_t valoreReset){ 
	__HAL_TIM_URS_ENABLE(htim);
	htim->Instance->CR1 |=  TIM_CR1_UDIS_Msk;

 //	htim->Instance->EGR |= TIM_EGR_UG_Msk;
 //	__HAL_TIM_SET_COUNTER(htim, valoreReset);
 	htim->Instance->CNT = 0X0;

htim->Instance->CR1&= ~TIM_CR1_UDIS_Msk;
 	__HAL_TIM_URS_DISABLE(htim);
}

When this code run Channel1 (IC function is still running). Channel 2 is stopped (OC function). When Channel 2 restarts the interrupt routine is launched.

I attached the snaphots of my debug before and after the counter reset. 

Don't know why interrupt is still there since OC callback starts.

Best regards

he UG bit generates an update event UEV but without
setting the UIF flag (thus no interrupt is sent).

[Techn]

TIMx_DIER  -> UIF bit controls whether you get an interrupt when the update event happens

Bit 0 UIE: Update interrupt enable
0: Update interrupt disabled
1: Update interrupt enabled

But you need to enable the update event otherwise it will not update from shadow register.. so URS=0 to get the update event in case of setting ug=1

Bit 2 URS: Update request source
This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generate an update interrupt or DMA request if enabled.
These events can be:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt or DMA request if
enabled