How to enable QSPI PSRAM as data memory

Zhou JianQiang · ‎2024-09-26

Hi:

I use STM32L4P5RG with APS6404L-3SQR to develop GUI.

I want use QSPI PSRAM as data memory for GUI.

Now, I enable QSPI PSRAM as data memory as follows:

1.configure QSPI PSRAM , SPI with NVIC in CubeMX

2. add PSRAM (xrw) : ORIGIN = 0x70000000, LENGTH = 8M to LinkerScript.ld

3. add following to LinkerScript.ld again:

   .ext_ram :
  {
    . = ALIGN(4);
    _ext_ram_start = .;        /* create a global symbol at ext_ram start */
    *(.ext_ram)         /* .ext_ram sections */
    *(.ext_ram*)        /* .ext_ram* sections */
    . = ALIGN(4);
    _ext_ram_end = .;         /* define a global symbols at end of ext_ram */
  } >PSRAM

4.configure PSRAM to memory map mode after MX_OCTOSPI1_Init/MX_OCTOSPI2_Init

5.create one global array out of main function for GUI, will use later by pointer:

__attribute__((section(".ext_ram"))) static uint8_t buf_for_disp[153600];

6.create two static arrays in main function for GUI, will use later by pointer:

    __attribute__((section(".ext_ram"))) static uint8_t buf_1[153600];
    __attribute__((section(".ext_ram"))) static uint8_t buf_2[153600];

7.later, SPI data will transfer to TFT by SPI DMA, the data is stored in arrays above.

The question is:

1. Should I enable NVIC for QSPI in CubeMX? If Yes, which value should the priority be (I don't use RTOS now, but maybe use later)?

2. Is this flow correct? Do I miss anything?

3. At first, the GUI work correctly, but after serval hours, the GUI can't display anything. I think the data in arrays is incorrect or the pointer address is wrong, but I don't know how to analyze this, because at first everything is OK, can you give me some advice?

KDJEM.1 · ‎2024-10-07

Hello @Zhou JianQiang ,

> I am on vacation and will reply to you within next week, but according to picture below, isn't the clock on the bus 60M?

The Reference manual detailed the "Bits 7:0 PRESCALER[7:0]: Clock prescaler". This field must be between 0 and 255 and defines the scaler factor for generating the CLK based on the kernel clock (value + 1).

In STM32CubeMX, the Clock Prescaler must be between 1 and 256. In this case the Clock Prescaler = (PRESCALER[7:0]: Clock prescaler)+ 1

Please see this FAQ:

Happy vacation, and I am waiting for your update.

I hope these recommendations will solve your issue.

Thank you.

Kaouthar

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

View solution in original post

Zhou JianQiang · ‎2024-09-27

Hi @SofLit @FBL :

Can you help confirm my question?

KDJEM.1 · ‎2024-09-30

Hello @Zhou JianQiang ,

You can enable NVIC for QSPI in STM32CubeMX. The priority value can depend on your application requirements, if the QSPI interrupt is not a time-critical compared to other interrupts you can set a lower priority.

Are you respect the conditions mentioned in STM32L4P5 errata sheet and precisely for memory mapped and DQS conditions?

Which frequency are you use for OCTOSPI?

Could you please check the OCTOSPI configuration and precisely Chip select boundary (CSBOUND). Please refer to AN5050 and precisely Table 8. STM32CubeMX - Configuration of OCTOSPI parameters, may help you for checking OCTOSPI configuration.

Also, may these videos can help you to set OSPI flash memory .

- STM32 Graphics: How to set up a different OSPI flash memory in a TouchGFX template, Part 1

- STM32 Graphics: How to set up a different OSPI flash memory in a TouchGFX template, Part 2

- STM32 Graphics: How to set up a different OSPI flash memory in a TouchGFX template, Part 3

Thank you.

Kaouthar

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

Zhou JianQiang · ‎2024-10-01

Hi @KDJEM.1 ：

>You can enable NVIC for QSPI in STM32CubeMX. The priority value can depend on your application requirements, if the QSPI interrupt is not a time-critical compared to other interrupts you can set a lower priority.

--> If I only use QSPI memory map(not DMA mode), is it necessary to enable NVIC? I try to blink LED in NVIC callback, but nothing happen, so I think maybe I don't need enable NVIC?

>Are you respect the conditions mentioned in STM32L4P5 errata sheet and precisely for memory mapped and DQS conditions?

--->Yes, I enabel DQS pin even though I don't have this pin. So memory map mode works, the problem is after several hours, it doesn't work correctly

>Which frequency are you use for OCTOSPI?

-->60M, you can refer pictures below for details, OCTOSPI1 for Nor flash W25Q128, OCTOSPI2 for PASRAM APS6404L

>Could you please check the OCTOSPI configuration and precisely Chip select boundary (CSBOUND). Please refer to AN5050 and precisely Table 8. STM32CubeMX - Configuration of OCTOSPI parameters, may help you for checking OCTOSPI configuration.

-->I use OCTOSPI multiplexed mode as above, so I think it is different from the AN5050

>Also, may these videos can help you to set OSPI flash memory .

- STM32 Graphics: How to set up a different OSPI flash memory in a TouchGFX template, Part 1

- STM32 Graphics: How to set up a different OSPI flash memory in a TouchGFX template, Part 2

- STM32 Graphics: How to set up a different OSPI flash memory in a TouchGFX template, Part 3

--> I think the key is PSRAM, not flash memory, but I will watch the video for reference.

KDJEM.1 · ‎2024-10-02

Hi @Zhou JianQiang,

Thank you for sharing these details.

> 60M, you can refer pictures below for details, OCTOSPI1 for Nor flash W25Q128, OCTOSPI2 for PASRAM APS6404L

--> Clock Prescaler: You set the prescaler to 1 in STM32CubeMx,. This means the clock on the bus is 120MHz / 1 = 120MHz. This behavior is detail in AN5050 and in this FAQ How to set up the OSPI peripheral to interface with the IS25LX256 from ISSI

Please refer to STM32L4P5 datasheet and check the maximum OCTOSPI frequency.

Please try to decrease the OCTOSPI frequency and let me know if the issue is solved or not?

Sample shifting (SSHT) should be enabled in STR mode and disabled in DTR mode. Delay hold quarter cycle (DHQC) should be enabled in DTR mode and disabled in STR mode.

Chip select boundary (CSBOUND) is configured depending on the memory datasheet and required for RAM memory. The chip select must go high when crossing the page boundary (2^CSBOUNDbytes defines the page size). In the PSRAM the page size is equal to 1024. So, CSBOUND=10.

Please take a look at Overall FAQs for QUADSPI/OCTOSPI/HSPI/XSPI - STMicroelectronics Community FAQ.

> the problem is after several hours, it doesn't work correctly

--> Do you get a corrupted data, HardFault....?

Please, make sure that you perform only 32-bit read accesses to the OCTOSPI memory.

Are you able to read and to write correctly when disabling graphic application?

Thank you.

Kaouthar

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

Zhou JianQiang · ‎2024-10-05

Hi @KDJEM.1 :

Thank you for your reply.

>Please try to decrease the OCTOSPI frequency and let me know if the issue is solved or not?

-->I am on vacation and will reply to you within next week, but according to picture below, isn't the clock on the bus 60M?

>Sample shifting (SSHT) should be enabled in STR mode and disabled in DTR mode. Delay hold quarter cycle (DHQC) should be enabled in DTR mode and disabled in STR mode.

>In the PSRAM the page size is equal to 1024. So, CSBOUND=10.

-->I will modify as your suggestion.

>Do you get a corrupted data, HardFault....?

-->No. I don't find any obvious fault after this occur.

>Please, make sure that you perform only 32-bit read accesses to the OCTOSPI memory.

-->How can I make sure? I don't know what should I do after I enable memory map mode to make sure I perform only 32-bit read accesses to the OCTOSPI memory.

>Are you able to read and to write correctly when disabling graphic application?

-->Without graphic application, I haven't tested for so long. But when I initialize PSRAM, I will run code below, and the printf won't run.

static const uint8_t qspipsram_test_data[] = {
    0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x07, 0x06,
    0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16,
    0x2F, 0x2E, 0x2D, 0x2C, 0x2B, 0x2A, 0x29, 0x28, 0x27, 0x26,
    0x3F, 0x3E, 0x3D, 0x3C, 0x3B, 0x3A, 0x39, 0x38, 0x37, 0x36,
};

__IO uint8_t *mem_addr = (__IO uint8_t*) (OCTOSPI2_BASE);
for (int var = 0; var < sizeof(qspipsram_test_data); ++var)
{
    *mem_addr = qspipsram_test_data[var];
    mem_addr++;
}

mem_addr = (__IO uint8_t*) (OCTOSPI2_BASE);
for (int index = 0; index < sizeof(qspipsram_test_data); index++)
{
    if (*mem_addr != qspipsram_test_data[index])
    {
        printf("qspipsram i:%02d:0x%02x not same", index, qspipsram_test_data[index]);
        break;
    }
    mem_addr++;
}

KDJEM.1 · ‎2024-10-07

Hello @Zhou JianQiang ,

> I am on vacation and will reply to you within next week, but according to picture below, isn't the clock on the bus 60M?

The Reference manual detailed the "Bits 7:0 PRESCALER[7:0]: Clock prescaler". This field must be between 0 and 255 and defines the scaler factor for generating the CLK based on the kernel clock (value + 1).

In STM32CubeMX, the Clock Prescaler must be between 1 and 256. In this case the Clock Prescaler = (PRESCALER[7:0]: Clock prescaler)+ 1

Please see this FAQ:

Happy vacation, and I am waiting for your update.

I hope these recommendations will solve your issue.

Thank you.

Kaouthar

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

Zhou JianQiang · ‎2024-10-09

Hi @KDJEM.1 :

Thank you for your help.

After I set Clock Prescaler from 1 to 2 in Cubemx and CSBOUND to 10, I tested it for 8 hours continuously, it works correctly, so I think this problem should be fixed.

But can you help answer question below:

1. If I only use QSPI memory map(not DMA mode), is it necessary to enable NVIC?

2. How can I make sure I perform only 32-bit read accesses to the OCTOSPI memory?

3. According to reference manual, it seems that Sample shifting (SSHT) can be disabled in STR mode, is it correct?

KDJEM.1 · ‎2024-10-09

Hello @Zhou JianQiang ,

Thank you for updating post and glad to know that the issue is solved.

>1. If I only use QSPI memory map(not DMA mode), is it necessary to enable NVIC?

--> If you use only QSPI (no interrupt or no DMA modes), it isn't necessary to enable NVIC.

>2. How can I make sure I perform only 32-bit read accesses to the OCTOSPI memory?

--> I mean use uint32_t data types for variables and read this from the OCTOSPI memory.

3. According to reference manual, it seems that Sample shifting (SSHT) can be disabled in STR mode, is it correct?

--> Yes, in SDR mode and when SSHIFT = 0 in OCTOSPI_TCR by default the signals are sampled using the following (rising) edge of CLK as mentioned in reference manual.

So, the SSHIFT can be enabled when reading from the memory in SDR mode but must not be used in DTR mode. When enabled, the sampling is delayed by one more 1/2 OCTOSPI/HSPI/XSPI clock cycle enabling more relaxed input timings.

If your issue is solved and your request is answered please click on Accept as Solution on the reply which solved your initial issue or answered your question.

Thank you for your contribution in STCommunity.

Kaouthar

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

Zhou JianQiang · ‎2024-10-14

Hi @KDJEM.1 :

After I test several times, I can reproduce this.

Do you have any further advice? I also enable SSHT, but it still can be reproduced.

I also notice that I2C will return HAL_ERROR after this happened(confirmed by Uart log, when this happened, Uart can still print log), but i am not sure they're related.