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STM32F411 cant get PLL to stabilize using HSI

cpalmer54
Associate II

Hi,

I seem to behaving an issue getting my STM32F411  PLL to stabilize using the HSI. The code I am using shown below. Setting it to 100MHZ.  The code gets stuck in RCC_GetSYSCLKSource() != 0x08 ) continue; . It never returns 8.  I had originally got stuck at while( RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET ) continue;

until added the flash wait state. Any ideas what I am doing wrong. I have run out of ideas at the moment. Any help much appreciated. Thanks Clive

 

RCC_DeInit();

//FLASH->ACR = FLASH_ACR_ACC; // 64-bit access
FLASH->ACR |= FLASH_ACR_LATENCY_1WS; // two wait states
FLASH->ACR |= FLASH_ACR_PRFTEN; // prefetch enable
FLASH->ACR |= FLASH_ACR_ICEN; // instruction cache enable
FLASH->ACR |= FLASH_ACR_DCEN; // data cache enable

RCC_HSEConfig(RCC_HSE_OFF);
RCC_HSICmd(ENABLE);
while( RCC_GetFlagStatus(RCC_FLAG_HSIRDY) == RESET);
// PLL_M = 16, PLL_N 400, PLL_P = 4, PLL_Q = 9
RCC_PLLConfig(RCC_PLLSource_HSI, 16, 400, 4, 9); 
RCC_SYSCLKConfig( RCC_SYSCLKSource_PLLCLK ); // Use PLL as system clock
RCC_PLLCmd( ENABLE ); // Enable PLL
while( RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET ) continue; // Wait till PLL is readywhile( RCC_GetSYSCLKSource() != 0x08 ) continue; // Wait till PLL is stable

RCC_HCLKConfig(RCC_SYSCLK_Div1); // HCLK = SYSCLK = 100MHZ
RCC_PCLK1Config(RCC_HCLK_Div2); // PCLK1 = HCLK/4 APB1 - 50Mhz
RCC_PCLK2Config(RCC_HCLK_Div1); // PCLK2 = HCLK/4 APB2 - 100Mhz

1 ACCEPTED SOLUTION

Accepted Solutions
STOne-32
ST Employee

Dear @cpalmer54 ,

You need to ensure that internal voltage V12 is set to Power Scale1: Regulator ON,
VOS[1:0] bits in PWR_CR register = 0x11 to be able to run up 100MHz.

Having 2 wait states of Flash is not enough, See table 15 Here Datasheet - STM32F411xC STM32F411xE - Arm<Sup>®</Sup> Cortex<Sup>®</Sup>-M4 32b MCU+FPU, 125 DMIPS, 512KB Flash, 128KB RAM, USB OTG FS, 11 TIMs, 1 ADC, 13 comm. interfaces   if your VDD is 3.3Volts, 3 wait states are required at least.

also please share your schematics and in particular if the VCAP pin with the External right capacitor. you can see voltage level at that pin to see 

STOne32_0-1730450991372.png

Hope it helps.

STOne-32.

View solution in original post

7 REPLIES 7
STOne-32
ST Employee

Dear @cpalmer54 ,

You need to ensure that internal voltage V12 is set to Power Scale1: Regulator ON,
VOS[1:0] bits in PWR_CR register = 0x11 to be able to run up 100MHz.

Having 2 wait states of Flash is not enough, See table 15 Here Datasheet - STM32F411xC STM32F411xE - Arm<Sup>®</Sup> Cortex<Sup>®</Sup>-M4 32b MCU+FPU, 125 DMIPS, 512KB Flash, 128KB RAM, USB OTG FS, 11 TIMs, 1 ADC, 13 comm. interfaces   if your VDD is 3.3Volts, 3 wait states are required at least.

also please share your schematics and in particular if the VCAP pin with the External right capacitor. you can see voltage level at that pin to see 

STOne32_0-1730450991372.png

Hope it helps.

STOne-32.

SofLit
ST Employee

Hello @cpalmer54 and welcome to the community,

You seem still using an older Standard Library for F4 need to migrate to STM32CubeF4 that you can download from this link.

To give better visibility on the answered topics, please click on "Accept as Solution" on the reply which solved your issue or answered your question.

 

> You need to ensure that internal voltage V12 is set to Power Scale1: Regulator ON,
VOS[1:0] bits in PWR_CR register = 0x11 to be able to run up 100MHz.

Please note that in order to change PWR registers, you need to swtich on PWR module's clock in RCC first.

JW

Thanks you. I think it would have taken me a long time to consider looking at this. I will look into it and report back. Schematic snippet enclosed. I have 2.2uF caps on the VCAP pins.

cpalmer54_0-1730700072023.png

 

Hi,

Thanks for the reply. I dont tend to use Cube. I'm a bit old school. 

Thanks JW, I'm going to try this later.

cpalmer54
Associate II

That has done the trick. I'm very grateful for the help. Thanks for taking the time to reply.