GPIO Trouble on STM32 F767ZI

[akash_praan]

I used a Nucleo F767ZI dev board to check and write firmware
(The IC on the board is STM32F767ZIT6U with the other characters being AA 254 VQ Z on first line and TWN AA 341 on line 2),
when I use HSI clock I am able to operate PD7, PG9, PG10, PG11, PG12 as an input or output GPIOBut on the custom developed board (the IC on the board is STM32F767ZIT6 with the other characters being AA108 VQ on the first line and TWN AA 334 on line two)

In this custom developed board while I am able to Program and debug the board and I am able to use all other pins except PD7, PG9, PG10, PG11, PG121)

1)The DC resistance of each of the above mentioned Pin and VCC(3V3) is infinite and same is with GND is also infinite
2) When I configure any of these Pins as GPIO Output as PUSH PULL and low speed mode then I see when I set the GPIO I see as the ODR setting but when I measure the voltage on the connecter(nothing between the connecter and the MCU Pin and tack length is less than 5 cms) i see 0.5 to 0.6V
3) When I configure any of these pins as Input with no Internal Pull or Pull Down, I see that these pins are not affected by noise where as other working pins are and if I connected 3V3 from a jumper cable to read input as logic High even that fails other than these 5 pins all other pins are working as expected.

Please help to debug the issue.

[akash_praan]

Hello, you are right, but the KiCAD symbol just gave one VSS(and somewhere on the web it mentioned it's all internally connected)

Nonetheless, let me check on the hardware if all VSS pins are actually connected to GND or not.

[akash_praan]

After the VDDSDMMC being connected, all pins work as intended. This was the error

VSS is internally connected as I verified in the Layout as well as the Hardware. 

Thank you for your help @Chris21 @Andrew Neil @LCE @Richard Li 

[Chris21]

Not sure what you mean by: "VSS is internally connected".

ST's guidance:

All the power supply and ground pins must be properly connected to the power supplies.
These connections, including pads, tracks and vias should have as low impedance as
possible. This is typically achieved with thick track widths and, preferably, the use of
dedicated power supply planes in multilayer PCBs.

In addition, each power supply pair should be decoupled with filtering ceramic capacitors
(100 nF) and one single tantalum or ceramic capacitor (min. 4.7 μF) connected in parallel.
These capacitors need to be placed as close as possible to, or below, the appropriate pins
on the underside of the PCB. Typical values are 10 nF to 100 nF, but the exact values
depend on the application needs. Figure 23 shows the typical layout of such a VDD/VSS pair.

[LCE]

> Not sure what you mean by: "VSS is internally connected".

The PCB layout screenshot shows that the GND pins are connected to GND underneath the package.

And some CAD apps' schematic symbols do not show all VCC or GND pins. I hate that, and rather draw my own...