Generating 4 pulses with different frequencies using only one STM32-Timer (4 channel PFM)

[RA]

Hi,

the goal is to generate 4 pulses with a constant on time duration followed by 4 different but variable off times, i.e. a 4 channel pulse frequency modulation with one timer. The on time shall be identical on all channels, but the off times shall be different from channel to channel and shall be a multiple of the on time.

In an existing hardware design the 4 timer compare channel outputs of TIM3 are OR-ed together and the output of the OR is connected to TIM3_ETR input. The old design worked and shall now be ported to another new hardware but the original developper is not available any more.

Any ideas on how one could program TIM3 and its 4 compare channels to generate 4 different pulse frequency modulations?

Thanks!

Regards Roland

[Tesla DeLorean]

You'd likely need to babysit the TIM in an interrupt handler. Set it to maximal count, and chase the phase with the CCRx registers. Interrupt could perhaps drive pins, or use toggle mode.

Other method is to use a pattern buffer and use TIM/DMA to drive pins via GPIOx->BSSR

If the frequencies divide into each other you could use a static buffer, otherwise you could build out a sequence dynamically at HT/TC interrupts for the DMA.

[waclawek.jan]

I don't understand the question. Is one signal to be generated, with four pulses with various spaces apart; or several signals? What comes after the four pulses, do they repeat infinitely, is there any longer delay between bursts of fours pulses, or is it a one-off event perhaps triggered by some external event? And if the pulses are to continue infinitely, are there requirements to change the spaces durations, and if yes, how often or upon what stimuli? What exactly are the time periods you are talking about, in terms of timer clock/frequency?

Generally, IMO, weird pulse sequences are best handled by the timer modifying its own registers through DMA, in more intricate cases using the DCR/DMAR mechanism. Clive listed some of the other options; which is the best option really depends on the very details of the task. The original designer may have had a very valid reason why he chose to spend the pins and external circuitry.

JW

[RA]

Hi JW, Clive Two.Zero,

thanks for your quick answers!

The hardware has in total 9 PFM outputs which are on timer channel output pins, but these pins might also be used as GPIOs. So after reading your answers, I doubt that these signals are generated by timer outputs but more likely in GPIO mode.

The pulse repetition frequency varies from about 8 kHz up to about 570 kHz. The pulse high time is constant (875ns), the low duration changes with time. This is in deed a classical use case for the DMA as you guys said.

Still unclear is the reason for the "feedback" of up to 4 OR-ed together outputs to an input which confuses me. Maybe because the number of DMA channels (7) of the STM32 CPU is less than the number of PFM outputs (9) so one DMA has to serve multiple outputs.

Any further ideas on how to implement such a behaviour are welcome!

Roland

[waclawek.jan]

So, one output is single-frequency, the problem is just that you need 9 of them, right?

And you want to reuse the original hardware, or is this a redesign? In the latter case, you can perhaps find a mcu with 9 timers.

Which STM32 are we talking about, and what's the clock frequency?

What are the requirements to change the output pattern? Are the 9 frequencies fixed, or do they change in time; if the latter, how often and what is the allowable latency between the input stimulus and the change in the output pattern?

Has the mcu do something else too, or is its task only the generation of the PFM?

JW

[RA]

Yes, one frequency per output and in total 10 of them (one is currently unused, but there are configs which uses 10).

There will be a new hardware design, however the STMF303 which is doing the job with 72 MHz is extremely cost efficient for this application. So this is the preferred MCU. However the MCU type is not fixed to the F303.

The output pattern, i.e. the pulse pause time, needs to be changed in real-time according to a precalculated table. The application is a multi channel stepper motor controller with acceleration / deceleration and step counting. Beside that task the MCU needs to get commanded by an USART interface with an high baudrate in the range of 1 to 1.5 Mbit/s) and shall check position sensors (switches).

Roland

[Tesla DeLorean]

One DMA can drive a pattern on any/all 16-pins in a given GPIO Bank, the granularity of the TIM trigger being 875ns.

BSRR allows for selective pins to set high/low on any transaction.

I guess you'd have to review the design in the context of the code/programming of the TIM

[RA]

Ok, thanks. The design uses different pins on Ports A,B,C for the 9 (up to 10) outputs, i.e. with 3 timers which triggers 3 DMA channels each 875ns, one could probably do the job. I will need to think about how to separate the outputs which are served on the same port, i.e. how to dymanically generate the BSRR patterns in memory as each output has an independent stream on bit sets and resets.

[waclawek.jan]

I believe, there's no way to solve this in a generic way.

However, I believe there may be enabling simplifications available which won't impact functionality.

Namely, your frequencies span is 1:70. Within that, I can find enough large coprime numbers so that the generic case of 10 signals can't be made cyclical within the available RAM. In other words, you would need to regenerate the patterns as they are "played out", which is IMO impossible given you have 63 machine cycles per pattern.

On the other hand, if you restrict your frequencies to a select group, you'd be able to generate a relatively short pattern set, which being playing cyclically generate regular frequencies (another, but IMO worse, option is, to tolerate jitter within one signal, resulting from the truncation of the last period at the wraparound). You'd then have relatively free hands in creating the next pattern set. Say, your pattern set would be a few hundred of patterns, resulting in a sequence few hundreds of us long; you can play back that pattern several times while generating the next set of patterns. And I bet the frequencies for the ramps don't need to be updated faster than once in a few milliseconds, do they.

I believe in this simplified case, this could be pulled out both by Clive's favourite timer-triggered-DMA-to-port method, and my favourite timer-native DCR/DMAR method. The former may result in a few cycles of jitter in the final product due to bus contention, the latter yields cycle-precision but may be more DMA-intensive potentially impacting system performance.

I believe that processing time for generating the patterns may be significantly improved using handcrafted asm, as it's simple enough to be handled manually just repetitive; but I may be proven wrong by an ultrasmart compiler.

Megabit UART may sound impressive but in fact it's the total required throughput, the processing requirement for the parser/reply construction, and the required latencies, what really matters.

I don't know what "step counting" may entail.

Sounds like a fun project ;)

JW

[waclawek.jan]

... or, much much better...

Drop the 'F303, pick 'F373. It has 11 usable timers. The software will turn from nightmare to a breeze, and the difference in cost is not that big (and at least partially balanced with removing the external OR). With a bit of luck, you'd be even able to recycle the existing PCB.

JW