Hi there,
I have got an STM32H7B0 processor.
I would like to make a part of the AXI (main RAM of application) not cacheable so I don't need SCB_CleanDCache() before/after DMA write/read transaction.
But another part of the AXI RAM should be cacheable and be used with DCACHE for data optimized access to the internal framebuffers.
If I make the AXI RAM not cacheable via MPU (not cacheable, not shareable, not bufferable) and run into a atomic_fetch_add which uses DMB() a hard fault occurs.
std::atomic<int> g;
g++;
If I uncomment this code above, the whole application (including DMA, freeRTOS, DMA2D) runs without problems. If I set the AXI RAM as cacheable, the error does not occur.
Does anybody know why this happens?
The CPU dies here:
// return __atomic_fetch_add(&_M_i, __i, int(__m)); }
9000BD86 LDR R3, [R7, #20]
9000BD88 LDR R2, [R7, #16]
9000BD8A DMB ISH
9000BD8E LDREX R1, [R3] // <-- hard fault
9000BD92 ADD.W R0, R1, R2
9000BD96 STREX R12, R0, [R3]
9000BD9A CMP.W R12, #0
9000BD9E BNE 0x9000BD8E ; <std::__atomic_base<int>::operator++>+0x1E
9000BDA0 DMB ISH
9000BDA4 MOV R3, R
