About TNeub.1

TNeub.1 · 2023-02-20

Hello,I saw a not yet reproducable fault at adresses, which are part of the private/vendor-specific memory regions.The fault happend on a STM32H7B0 runnig freeRTOS, ICache + DCache enabled:Causing instruction address: 0x7.... (external flash)Comming ...

TNeub.1 · 2022-06-17

Hello,currently we are successfully using an external NOR flash connect via Hyperbus on OCTOSPI1, ClockPort 1 for some time (~1.5 year).We would like to switch to OCTOSPI2 because we want to use the other address area (0x70000000UL instead of 0x90000...

TNeub.1 · 2022-02-18

Helloare there any plans for supporting a specific TouchGFX version for many years like a LTS version?Best regard.

TNeub.1 · 2022-02-12

Hi there,I have got an STM32H7B0 processor.I would like to make a part of the AXI (main RAM of application) not cacheable so I don't need SCB_CleanDCache() before/after DMA write/read transaction.But another part of the AXI RAM should be cacheable an...

TNeub.1 · 2021-11-03

Im unsure how TouchGFX know if the current touch event is a "click" or a "long press" or a swipe - if it only gets the current position?https://support.touchgfx.com/docs/api/classes/classtouchgfx_1_1_touch_controller#function-sampletouchDo I need ano...

TNeub.1 · 2023-03-15

Hello,thank you for your answer.LR was 0xE0059256, the PPB....

TNeub.1 · 2023-02-27

No, only the valid bit of the busfault register.

TNeub.1 · 2023-02-27

This is content of the LR register.

TNeub.1 · 2023-02-26

Well, thank you but I know what the map file is for.So ST will not let us/me know, which internal peripheral (like the ICache?) is on these memory addresses? Since they are causing trouble in this case and knowing what they are used for could help to...

TNeub.1 · 2023-02-23

Hello,thank you for your reply.I cannot share any of these files since it is a commercial project. I also don't think the map file would be of any help. There aren't any symbols at 0xE...(since this is ARM/ST memory regions).I sadly cannot reproduce ...

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Mem/BusFault at internal memory regions (0xE0...)

Switch from OctoSPI1 to OctoSPI2

Long time support

DMB() in atomic_fetch_add leads to hard fault if MPU AXI is not cacheable

How does sampleTouch(..) can distinguish between touch clicks and long touches and swipes?

Re: Mem/BusFault at internal memory regions (0xE0...)

Re: Mem/BusFault at internal memory regions (0xE0...)

Re: Mem/BusFault at internal memory regions (0xE0...)

Re: Mem/BusFault at internal memory regions (0xE0...)

Re: Mem/BusFault at internal memory regions (0xE0...)