DMA mapping for STM32F407 series

[tinkerer_of_universe]

What is the meaning of These requests are available on STM32F42xxx and STM32F43xxx only for DMA1 and These requests are available on STM32F42xxx and STM32F43xxx for DMA2.
What should ı use for the mapping ?

 

[Andrew Neil]

For some reason, the forum can't display your image:

Note that you can just paste straight into the post so that the image is immediately visible.

[tinkerer_of_universe]

Thank you ı fix the image

[SofLit]

Hell @tinkerer_of_universe and welcome to the community,

For example, if you want to trigger DMA transfer using ADC3 end of conversion, you need to select Stream 0 / Channel 2.

Example from HAL:

hdma_adc.Instance = DMA2_Stream0;
hdma_adc.Init.Channel = DMA_CHANNEL_2;

For more details, please review the AN4031  "Using the STM32F2, STM32F4 and STM32F7 Series".
DMA controller 

Figure 1. DMA block diagram

[tinkerer_of_universe]

Which channel should I choose for transferring CDR register data?
also
Does this sentence have no relevance to STM32F407
These requests are available on STM32F42xxx and STM32F43xxx only for DMA1 and These requests are available on STM32F42xxx and STM32F43xxx for DMA2.

[SofLit · Accepted solution]

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@tinkerer_of_universe wrote:

Which channel should I choose for transferring CDR register data?

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CDR on which ADC? as I said, each one has its channel and stream as shown in the table.

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@tinkerer_of_universe wrote:

Does this sentence have no relevance to STM32F407
These requests are available on STM32F42xxx and STM32F43xxx only for DMA1 and These requests are available on STM32F42xxx and STM32F43xxx for DMA2.

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This note is related to some peripheral mappings:

So these requests are available only on STM32F42xxx and STM32F43xxx products.

[tinkerer_of_universe]

Thanks

ı use dual ADC mode and ı want to carry 2 data(ADC1 and ADC2) with DMA at the same time that is why ı want to use CDR register

[SofLit]

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@tinkerer_of_universe wrote:

ı use dual ADC mode and ı want to carry 2 data(ADC1 and ADC2) with DMA at the same time that is why ı want to use CDR register

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In multimode (Example Dual mode)  ADC1 is master to the ADC2 and ADC3 slaves.

From the reference manual: 

So in that case DMA will get the request from ADC1, i.e. DMA2 Stream 0 / Channel 0 as per table 43.

You can also check this example (ADC in Dual mode) :

In main.h:

/* Definition for ADCx's DMA */
#define ADCxy_DMA_CHANNEL                DMA_CHANNEL_0
#define ADCxy_DMA_STREAM                 DMA2_Stream0 

Hope it's clear.

[tinkerer_of_universe]

Thanks for the ADC information. I understand more clearly than before. I chose Dual mode. I guess your suggestion is usable for Triple mode. However, I can't see how to transfer the CDR register data using Table 43. I want to use just one address (CDR), but the table includes ADC1, ADC2, and ADC3, which is why I'm confused.