Bare Metal STM32L496

[vbk22398]

void SystemClock_Config(void)
{
// Step 1: Enable HSI
RCC->CR |= RCC_CR_HSION; // Enable HSI
while (!(RCC->CR & RCC_CR_HSIRDY)); // Wait until HSI is ready

// Step 2: Configure the voltage scaling
PWR->CR1 |= PWR_CR1_VOS_0; // Set voltage scale to 1 (VOS = 1)

// Step 3: Configure the PLL
RCC->PLLCFGR = 0; // Clear PLL configuration register
RCC->PLLCFGR |= (1 << RCC_PLLCFGR_PLLM_Pos) | // PLLM = 1
(10 << RCC_PLLCFGR_PLLN_Pos) | // PLLN = 10 (HSI frequency * 10 = 80 MHz)
(0 << RCC_PLLCFGR_PLLP_Pos) | // PLLP = 2 (DIV2)
(2 << RCC_PLLCFGR_PLLQ_Pos) | // PLLQ = 2 (DIV2)
(2 << RCC_PLLCFGR_PLLR_Pos) | // PLLR = 2 (DIV2)
RCC_PLLCFGR_PLLSRC_HSI; // PLL source = HSI

// Step 4: Enable the PLL
RCC->CR |= RCC_CR_PLLON; // Enable PLL
while (!(RCC->CR & RCC_CR_PLLRDY)); // Wait until PLL is ready

// Step 5: Set PLL as the system clock source
RCC->CFGR &= ~RCC_CFGR_SW; // Clear SW bits
RCC->CFGR |= RCC_CFGR_SW_PLL; // Set PLL as the system clock source
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL); // Wait until PLL is used as system clock

// Step 6: Configure the AHB and APB prescalers
RCC->CFGR &= ~RCC_CFGR_HPRE; // AHB prescaler = 1
RCC->CFGR &= ~RCC_CFGR_PPRE1; // APB1 prescaler = 1
RCC->CFGR &= ~RCC_CFGR_PPRE2; // APB2 prescaler = 1

// Step 7: Configure flash latency
FLASH->ACR &= ~FLASH_ACR_LATENCY; // Clear latency bits
FLASH->ACR |= FLASH_ACR_LATENCY_4WS; // Set latency to 4 wait states for 80 MHz
}

The code doesn't break out of while loop.
I am struck in the step 5. unable to resolve the issue.
// Step 5: Set PLL as the system clock source. Help me resolve this issue.

[waclawek.jan]

You have to set APB prescalers, and, more importantly, the FLASH waitstates, *before* you switch the system clock to PLL in RCC_CFGR.

JW

[gbm]

PWR must be enabled in RCC before use.

[waclawek.jan]

> PWR must be enabled in RCC before use.

Correct; however, Range 1 is the default VOS setting anyway.

JW

[gbm]

Also, the value written to PLLM, PLLP, PLLQ and PLLR fields is the divisor value - 1.

You may find the working clock setup code in my USB stuff, link in signature - Example/Inc/L4 folder.

[waclawek.jan]

In the mid-range 'L4, the Q and R dividers are 2 * (value + 1), and P is quite bizarre, 7 or 17...  and HSI frequency is 16MHz. These things tend to change from STM32 to STM32 (sub)family.

> link in signature

I don't see any signature in this thread (https://community.st.com/t5/stm32-mcus-products/bare-metal-stm32l496/m-p/734800 ).

JW

[SofLit]

Hello @vbk22398 ,

In next time please use </> button to post your code. See these tips on posting a thread.

Thank you for your understanding.

[Andrew Neil]

---

@waclawek.jan wrote:

> link in signature

I don't see any signature

---

Here:

[waclawek.jan]

Interesting. I don't see it.

But by this point I gave up any attempts to comment on the state of affairs; it's just waste of time and energy. I have better places to be ignored.

JW