STM32 MCUs

Hello everyone, I'd like to use the LevelX API with FreeRTOS on an STM32H5 microcontroller. I know that LevelX is typically used with AzureRTOS, but I'd like to know if ST provides any guidance on integrating it with FreeRTOS or if anyone has any suggestions on how I can do this. Thanks for your help.

While driving PMSM motor using STM32303E-Eval with IPM20B driver card, Motor is jerking and spinning abnormaly. I am using sensored feedback method such as encoder having 1024 ppr. 

Hi!I'm struggling to wrap my head around timers - I am trying to schedule some ADC reads of a current sense amplifier in a motor control setup.I have three center-aligned PWM waveforms being generated by Timer1, which successfully commutate a BLDC motor. That's great. I would now like to schedule an ADC read once per PWM period. A simple first try at this would involve a single read right in the center of the PWM waveform. A slightly swankier version would be to calculate the largest duty cycle of my three PWM phases, and schedule my ADC read just after this point (but, again, just once per PWM period). I have experimented with configuring Timer1's TRGO to "Update Event", and scheduling my injected ADC read to be "Timer 1 Trigger Out Event". This, however, schedules the read at the beginning of the PWM period, rather than in the center of it. I'm also experimenting with setting up a slave timer - the idea being to trigger this secondary timer based on the above Timer1 TR

BOARD: STM32H743IITXACTICLE FOLLOWED: https://community.st.com/t5/stm32-mcus/how-to-implement-a-usb-device-composite-in-stm32h5/ta-p/708078Hello everyone,I was trying to use USB CDC+MSC in composite mode. After following the article mentioned above, i was able to build the project. But after running i was able to only get MSC (as shown in pc) and getting the CDC port with windows error 10.Few things i have changed, in usbd_desc.c updated these lines   0xEF, /* bDeviceClass */ 0x02, /* bDeviceSubClass */ 0x01, /* bDeviceProtocol */ Also i have updated CDC_IN_EP, CDC_OUT_EP, CDC_CMD_EP so it should not match MSC_EPIN_ADDR and MSC_EPOUT_ADDR     #ifndef CDC_IN_EP #define CDC_IN_EP 0x82U /* EP1 for data IN */ #endif /* CDC_IN_EP */ #ifndef CDC_OUT_EP #define CDC_OUT_EP 0x02U /* EP1 for data OUT */ #endif /* CDC_OUT_EP */ #ifndef CDC_CMD_EP #define CDC_CMD_EP 0x83U /* EP2 for CDC commands */ #endif /* CDC_CMD_EP */ #ifndef MSC_EPIN_ADDR #define MSC_EP

On the STM32C542RC, this is my current FLASH layout:-- OEMiRoT flash layout:-- Bootloader : 0x08000000 .. +0x10000-- Keys : +0x10000 (0x2000)-- NV counters : +0x12000 (0x2000)-- Primary app slot : 0x8014000 size=0x16000-- App code (post-hdr) : 0x8014400 size=0x15c00-- Secondary app slot : 0x802a000 size=0x16000-- OEMiRoT option bytes to program:-- HDP1_END = 0x9 WRPSGn1 = 0xfe00Everything is working well (update of user application, boot, etc...) (MCUBOOT_USE_HASH_REF is not defined).But I have an issue:I want to use the external User Data Flash at the address FLASH_EXT_USER_BASE 0x08400000UL, requiring the option byte EDATA_EN = 0. When I read from that address in the User Application, I only read zeroes (RAZ) -- simple as `*(const int *)FLASH_EXT_USER_BASE == 0`, so this feels like the cause is some sort of HDP. By the way, the writes do work (at least when the MCU is reset, as STM32CubeProgramm

I was trying to configure ethernet on my android phone via using usb cdc ncm on stm32 nucleo U5A5 and i was unable to see the ethernet option in the network settings of the phone.It was completely greyed out. I tried the same on ios and i was able to connect via ethernet. What am i supposed to do to resolve this ?im using ncm of tiny usb for this connectivity.

Hello,I am using an STM32F207VC custom board with Ethernet and LwIP. I am facing an issue related to Ethernet cable connection during power-up.I performed the following tests:Test A: Ethernet cable connected before power ONConnect the Ethernet cable.Power ON the STM32 board.Result:Ping: WorkingTCP server connection: WorkingTest B: Ethernet cable disconnected during power ONDisconnect the Ethernet cable.Power ON the STM32 board.Wait until all STM32, Ethernet, and LwIP initialization is completed.Connect the Ethernet cable.Result:PHY Link Up: DetectedPing: WorkingTCP server connection: Not workingTest C: Cable disconnect and reconnect after normal startupStart the board with the Ethernet cable connected.TCP server works normally.Disconnect the Ethernet cable.Reconnect the Ethernet cable.Result:Ping: WorkingTCP server connection: WorkingThe issue occurs only when the STM32 board is powered ON while the Ethernet cable is disconnected and the cable is connected later.Since ping works and th

Hi, I wrote a flash bootloader for STM32G070 using IAR ide.It gets via modbus RTU the command/data to manage the FSM that does the update procedure.Because the master during erasing/programming needs a real time update on overall progression, the .intvec table, the main, the modbus stack and the updaing FSM are all relocated in RAM.With firmware in RAM and a management of FLASH delete/program via IT the firmware can handle modbus during flash programming.The .intvec relocation is done programmtically, copying it from FLASH (0x08000000) to RAM (0x20000000)  (0xB8 bytes):  I did via explicit firmware because I’m not able to do it via .icfAlso relocated in RAM  stm32g0xx_hal_flash*.o via “initialize by copy” in .icf.VTOR set to 0x20000000main entry point and other self-made function as well as modbus stack’s  marked as __ramfunc.Great, you say, if everyhing works why this topic? The truth is: to do all above I did a workaround  because a problem came when I linked HAL_FLASH_IRQHandler.Wit

Can we flash same hex file in STM32xxxxVJT6 and STM32xxxxVJT3.

Part Number: STM32F427VIT6Environment: Custom PCB (not an eval/dev board), native SDIO/SDMMC1 peripheral, 4-bit bus, FatFs (ChaN's ff.c) on top of ST's HAL (stm32f4xx_hal_sd.c). STM32CubeIDE 2.2.0, GNU Arm Embedded toolchain 14.3.rel1 (arm-none-eabi-gcc), STM32CubeProgrammer for flashing/SWD debug, bare-metal HAL (no RTOS). SDIO clock tested from 400kHz up to ~24MHz; same result throughout.Schematics / hardware note: This is a custom PCB, so a board-level cause can't be fully excluded, a scope check on the 3.3V rail during a write burst is still pending, and I'm happy to attach the relevant SDMMC1/power schematic on request. That said, a pure PCB signal-integrity/trace defect looks unlikely specifically: DAT0-3 are bidirectional and reads over those same physical traces are 100% reliable, every write's CRC check passes cleanly, the failure is fully deterministic rather than marginal/intermittent, and it's unchanged across the full 400kHz-24MHz clock range tested, none of that fits a ti

I’ve trawled through several CRC-related threads without finding an explanation of this: How to properly set up bit reversal.Normally, I use CRC-16 XMODEM, which uses the 0x1021 polynomial and no bit reversal. This works perfectly fine when I use this code:void xmodemCalcCRC (uint8_t Data, uint16_t *CRCVal){ CRC->POL = 0x1021; // CRC polynomial CRC->INIT = *CRCVal; // Previous CRC result CRC->CR = CRC_CR_POLYSIZE_0; // 16-bit polynomial *(__IO uint8_t*)(&CRC->DR) = Data; // Feed an 8-bit value into the algorithm *CRCVal = CRC->DR; // Read the result}The reason I set the polynomial, the initial value and configuration every time is to accommodate different CRC methods in the same application.Now, in a current project (using an STM32L433 microcontroller) I need to use CRC-16 Kermit as well. According to crccalc.com, Kermit CRC uses bit reversal on input and output. This is where my trouble begins: When bit revers

Hi.I'm trying out new STM32N6 Nucleo board. It has cmera interfaces, so I wanted to try some examples with the camera.My usual routine for quickstarting some new STM32 product was to download CubeMX package for it, go to Repository folder -> Projects -> [board] -> Applications or Examples, and run an exaple project. But I didn't find any example neather for Nucleo nor other boards.Where can I find camera examples for NUCLEO-N657 board?Thanks.

In Table 7.4, "Low-power mode wake-up timings on LDO" of the datasheet, there is no mention of the FSTEN setting in the conditions for twu(stop3)​ (wake-up in SRAM2). When waking up in SRAM2, is the wake-up time typ. 22.5 μs at MSI=24MHz regardless of the FSTEN setting?

Dear ST Community,I am working on an STM32 motor control project using MC Workbench and would like to configure one SPI interface and two UART interfaces in addition to the motor control peripherals.Is it possible to configure SPI and two UARTs while using MC Workbench?I tried configuring these peripherals by modifying the generated .ioc file in STM32CubeMX. However, when I regenerate the project/code, some of the peripheral configurations are overwritten by the MC Workbench-generated configuration.Could you please suggest the recommended approach for this use case? Specifically:Is there a supported way to configure SPI + two UARTs directly through MC Workbench? If not, what is the recommended method to add these peripherals without their configuration being overwritten? Should the peripherals be configured in the .ioc file after MC Workbench code generation, or is there another recommended integration method? Are there any specific USER CODE sections, middleware, or configuration file

I have an application that uses internal flash for logging.  Unfortunately, after exiting stop3 subsequent writes to flash fail.  Here’s my exit code -- the names of the routines should give a general idea.  I don’t really have a clue what changed and the reference manual is notably sparse on details about the various stop/standby/shutdown modes  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); __DSB(); __WFI(); __ISB(); CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); PWR->APCR &= ~PWR_APCR_APC; palSetLine(LINE_testpin); chSysLock(); tagPowerRestoreClocksAfterStop3(); tagPowerPostStop3WakeEventI(); chSysUnlock(); // Ensure Flash is awake and not stuck in low-power mode FLASH->ACR &= ~(FLASH_ACR_SLEEP_PD); __DSB(); 

Hi,Could you please share example for using IIS2MDCTR via SAI on STM32U385.Thanks

As the title suggests, I see in debug mode that audio is captured from I2S_RX, but it is not transmitted on the transducer (I cannot hear any audio coming from I2S_RX with my hear). And the problem is that with the same hardware wiring it works on the other boards (including H7S3L8), but not on this specifically. I’ve tried to place dma buffer in RAM D2 and I’ve disabled D cache,  ut it does not solve anything. Is the board I’ve ordered broken? I upload the code below

Hi all,Are these available for these samples? I am working on some secure boot devices and would like to try these chips as I am familiar with the STM32 ecosystem. Are you guys have any suggestion which NUCLEO can use for secure-boot purpose?I see there are NUCLEO-H5xx are designed for hardware crypto, sample project and we can build for chain of trust from these family chips?Please let me know, thank you.

Hello,I am evaluating the EVSTDRVG611MC for a high-speed motor control application in Japan.The data brief describes the board as having a “230 V AC mains line input,” but I could not find the supported AC input voltage range for connector J4.Could you please clarify the following?What is the supported AC input voltage range for J4? Can the EVSTDRVG611MC be operated from 100 VAC, 50/60 Hz? If 100 VAC operation is possible, are there any restrictions on output power or motor operating conditions compared with 230 VAC? When supplied from 100 VAC, the rectified DC bus would be approximately 140 VDC at no load. Is this an intended/acceptable operating condition for the inverter?For reference, the target motor is approximately 130 W and rated for a 140 VDC bus, so I would like to understand whether direct 100 VAC input can be used for evaluation, or whether an external DC supply connected to J6 should be used instead.Thank you

Board: STM32N6570-DK Sensor: Sony IMX219 (Raspberry Pi Camera Module 2 / NoIR), custom driver, connected via a 15-pin-to-22-pin adapter cable into the board's camera connector (normally used for the MB1854/IMX335 module)SummaryI've written a from-scratch IMX219 driver (I2C register map transcribed from the Linux kernel's imx219.c) as an additive sensor option alongside the working IMX335 path. I2C control, power sequencing, and CSI-2 D-PHY link all come up healthy. DCMIPP's own status registers report that PIPE1 is continuously and successfully capturing new frames. But the actual pixel data written to memory is frozen — bit-for-bit identical — and does not respond to real scene changes. I'm looking for insight into what could produce this specific disconnect.Configuration2 CSI-2 lanes, D-PHY bitrate bucket DCMIPP_CSI_PHY_BT_900 (900 Mbps bucket, closest available to the computed 912 Mbps for this PLL config) Sensor PLL: VTPXCK_DIV=5, PREPLLCK_VT_DIV=3, PLL_VT_MPY=57, OPSYCK_DIV=1, PRE

Hi,I am using the STM32H745I-DISCO board and trying to boot an application from the external QSPI flash (MT25QL512ABB).For this purpose, I created two separate projects: Bootloader Project Initializes the QSPI flash. Configures the QSPI in Memory-Mapped mode. Jumps to the application stored in the external QSPI flash. Application Project Modified the linker script (.ld file) to change the application start address from 0x08000000 to 0x90000000. Added the following statements in CM7/Common/Src/system_stm32h7xx.c (around lines 295–296) inside SystemInit(): As a basic test, the application code is only trying to blink the LED connected to GPIO Pin 13 after booting from the QSPI flash. RCC->CFGR = 0; SCB->VTOR = QSPI_BASE;After building the application, I generated the .bin file and programmed it into the QSPI flash using STM32CubeProgrammer.When I read back the contents from address 0x90000000 using CubeProgrammer, I can see valid data programmed in the fla

Based on discussion here, conclusion is, that given in 'L45x/'L46x there's no DAC1_CH2, and in 'L41x/'L42x no DAC at all, these are unavailable for inputs selectable for COMP for these sub-families of the low-end 'L4xx family group handled collectively by RM0394. Description in stm32l4xx_hal_comp.c does not tell these completely, and there are also references to 'L43x/'L44x having some exceptions, which based on RM/DS doesn't appear to be the case:   Also, macros in stm32l4xx_ll_comp.c don't take the missing DAC channels into account, and they should. Can these be looked at, please. Thanks, JW

I am attempting to exist from a Shutdown mode using the WKUP6 pin (PB5) on an STM32G0B1CEU.This is my shutdown code.HAL_SuspendTick();__HAL_RCC_PWR_CLK_ENABLE();HAL_PWREx_EnableGPIOPullUp(PWR_GPIO_B, PWR_GPIO_BIT_5);HAL_PWREx_EnablePullUpPullDownConfig(); // sets the APC bit in PWR_CR3HAL_PWREx_EnablePORMonitorSampling();HAL_PWR_EnableWakeUpPin(PWR_WAKEUP_PIN6_LOW);// Do reads of registers to ensure they were written(void)PWR->CR3;(void)PWR->CR4;/* Clear all related wakeup flags*/__HAL_PWR_CLEAR_FLAG(PWR_FLAG_WUF);HAL_PWREx_EnterSHUTDOWNMode();This seems to do almost exactly what I would expect it to do.PB5 goes high.Power consumption drops.However, it never wakes up.  I have a wire connected to PB5, which I am measuring with a scope, and confirm that it is going high.  I am them shorting that wire to ground and confirm that it goes low.  The system doesn’t wake up. I know it’s not immediately going back to sleep because right now there is no automated way for it to enter sleep m

Hardware & Setup- MCU: STM32H523RE (I3C target/slave mode) - Controller: STM32H533RE (I3C controller mode)- HAL Version: STM32CubeIDE 1.16.1, HAL for STM32H5- Bus Speed: 3.205 MHz I3C SDR Problem Description We're implementing an I3C target that needs to respond to random address reads with repeated start: [START][ADDR_W][0x01][RESTART][ADDR_R][DATA][STOP] Where:- ADDR_W writes the address byte (0x01) to tell the target which register to read- RESTART signals the repeated start- ADDR_R begins the read phase- Target should respond with data from address 0x01 The problem: Loading the TX FIFO in the RXFNE interrupt handler doesn't work. The hardware transmits stale data before the ISR can fill the TX FIFO with the requested data. 1. RXFNE interrupt fires when address byte (0x01) is received2. ISR starts executing (~1-2µs interrupt latency)3. ISR flushes TX FIFO and writes fresh data to TDR registers4. But hardware has already started transmitting from the (empty/stale) TX FIFO The I3C

I’m working on a system design that incorporates gigabit Ethernet. I’ve been looking at using the STM32N6x7 family of parts to support this functionality. The product selector and datasheet seem to indicate that each package supports the 1000 Ethernet. In addition, the datasheet starts off by listing the gigabit Ethernet as a family supported technology. However, Tables 2 - 5 of the datasheet that list the variations in supported functionality between packages does not list Ethernet whatsoever on any package. To me this implies that the functionality is supported on all devices equally, otherwise the different protocols supported would be listed here.Figure 1: Example of Product Selector FilterFigure 2: Excerpt from Datasheet Listing 1 Gbit Ethernet Support for the STM32 Family Thus, I started with the smallest package for ease of routing and space consumption. However, when matching the device with an external gigabit Ethernet PHY as required, I noticed that there are signals that are