Can ST please quantify waitstates imposed by accessing ETH registers
ETH is obviously a dual-clock peripheral, and some of the registers are most probably behind a synchronizer, in the MII clock domain. It’s not unlikely that reading some of those registers imposes waitstates. Writing may not, but then those are subject to the Successive write operations to the same register might not be fully taken into account erratum (which hints at the fact that there’s a 4-MII-clock synchronization mechanism, at least for writing).
Can ST confirm or deny, whether reading and/or writing ETH registers imposes waitstates, and in case of yes, can ST please list related registers and also quantify number of waitstates. Here’s why.
In particular, we need this to be quantified for the ‘F4xx, but for other families it would be a bonus to have this, too.
Thanks,
JW