NUCLEO-N657X0-Q POWER_ON signal appears to be floating with bad effects

[GregBailey]

Hi, Folks.

I’m using a board with NUN code ending in $CR1, C260400252, MB...Q-C02 if that includes useful rev info.

I started powering this ST Nucleo board with +12 from a bench supply, limited at 600 mA, into CN3 pin 24 with ground on pin 20 (19,20,22 all ground) and that was being regulated down to +5 by U25 just fine.  So I let the board see the +5 by inserting CN9:5-6 jumper.

With nothing plugged in but power, LD1 was on (green), LD9 red on and green flashing, LD4 red on faintly, LD5 flashing red.  All this as expected except the state of LD9 which appeared to be due to 3V3_STLK existing (regulated from 5V) but no USB connection.  I checked and recorded all the voltages on CN2; everything looked reasonable except pins 9 and 10 pertaining to the internal SMPS which is free floating, because by default VDD1V8 is not being generated (low nonzero voltage at TP14).

I was about to plug the cable I’d made into CN1 when I noticed LD5 had stopped flashing and the current being drawn from my 12V supply was diminishing gradually. I tried several things like running 5V in thru each of the 2 USB ports and directly from a bench supply into CN9 pin 6, and finally back to 12V as it was at the beginning.  What I observed in each of these cases was that the 0.8V, 3.3V and 1.8V supplies were no longer present on CN12, and LD5 ("LED2") at lower right corner of the board was not flashing.

None of the board's regulators (except the 12V to 5V and the one making 3V3_STLK) appears to be working, although they did when I first powered the board.  Each of those regulators depends on the enable signal named PWR_ON, active high.  TP19, on the bottom side of the board, is at ground so the chip at the heart of this board does not see that enable either, although without VDDCORE it hardly matters.

What I do not find anywhere on the schematic is a discrete SOURCE of any kind for the PWR_ON signal other than perhaps residual leakage in chip input structures.  My only theory for this, so far, is that this net is floating and happened to have a charge when I started that was gradually lost during the several minutes while the board was working and flashing LD5 as it was intended to.  If that’s true, perhaps that floating net is getting charge from something else I was not yet doing.  (The TI data sheet on the TPS62088YFP regulator for the VDDCORE 0.81V supply specifically says not to leave its EN pin floating.)

If the schematic is correct, the only non-sink of PWR_ON is the yellow “PWR_ON” rectangle in the upper left corner of schematic page 9.  I do not see any signal output or connection point corresponding with this rectangle on the board, so I suspect the signal truly is floating and if the board works those power regulators are only running by accident.

If I don’t get knowledgeable advice here quickly, I plan to tack-solder a 10k pull-up between TP19 and the 5V rail, but would rather not put an iron to this board unless that’s the only way to fix it.

Any help would be greatly appreciated. - Greg

[RomainR.]

Hello ​@GregBailey 

I reproduced the same power supply configuration as yours, which is also documented in UM3417, Section 7.4 Power Supply, Figure 11: CN9 [5-6]: 5V_VIN power source. 
STM32N6 Nucleo-144 board (MB1940) - User manual

My NUCLEO-N657X-0Q ($CR1) is configured in DEV Boot mode (JP2 BOOT1 = 1) and powered as follows:

• An external power supply (7-12 VDC, 500 mA) connected to CN3 pin #24 = 7 V and pin #20 = GND.
• CN9 [5-6] configured accordingly.

The board status is:

• LD1 = ON, indicating that the 5 V rail generated by LDO U25 is present.
• LD2 (red LED) = ON, indicating that the STM32N6 BootROM has successfully started in DEV_BOOT mode.

Finally, I connect my STLINK-V3SET to the CN1 MIPI connector, and I can successfully establish an SWD connection using STM32CubeProgrammer. No issue in this case.

Now, with the same power supply configuration, but in Flash Boot mode (JP2 BOOT1 = 0 and JP1 BOOT0 = 0), the external NOR Flash contains firmware that toggles LD1 (blue user LED), and this also works as expected.

In both cases, the board operates perfectly, and I do not observe any issues.

Regarding your observation : PWR_ON output is in VDD domain of the STM32N6 (powered by VDDIO) and is used to enable the following power rails during the power up-sequence:

• VDDCORE (generated by DC/DC converter U17)
• VDDA1V8 (generated by LDO U26)
• VDD3V3 (generated by DCDC U34)

In contrast, VDD3V3, VDDIO, and VDDA18AON are continuously supplied from the 5 V rail generated by U25.

For PWR_ON to be driven high (3.3 V), both of the following conditions must be met :

• VDDA18AON must be above its corresponding POR threshold
• VDDIO must be above its corresponding POR threshold

The following test points should therefore be measured on your board:

• TP2: Main 5 V supply
• TP15: VDDA18AON = 1.8 V
• TP13: VDDIO = 3.3 V

If these voltages are not present, it is very unlikely that PWR_ON will become active and enable the corresponding regulators.

Your board may be defective or damaged (for example, U25 may be faulty).

I hope this information helps, let me know about your investigation and results.

Best regards,

Romain,

[GregBailey]

Thanks, Romain.  While what you said above about part designations (LD2 vs LD9, LD1 vs LD5 and color of same) doesn’t match what I see on my board or on the schematic, it truly does appear that U23 and U33 are blown (i.e. 5V in but 0.8V and 0V out).  I must have zapped them while probing the voltages on CN12.  I’d also failed to notice that PWR_ON is an output from the STM32N657 chip.  My bad both cases, appreciate your help.