STM32H7S78-DK + Infineon S28HS512T: erase reports success, but write times out polling WIP

[nico23]

I’m using an Infineon SEMPER NOR flash (JEDEC manufacturer ID 0x34; S28HS512T) with the STM32H7S78-DK XSPI2 interface. The bootloader uses STM32 External Memory Manager’s SFDP NOR driver, configured as EXTMEM_LINK_CONFIG_8LINES. The device has a hybrid sector map, and I’m updating mapped sectors from firmware stored on an SD card.

The updater compares each logical sector, erases sectors marked for update, then writes the corresponding firmware data. Block-protection setup reports success: CLPEF (0x82), writes to CFR3V and STR1V (0x71), and a DYB unprotect write (0xE1) all return HAL_OK.

For sector index 33, at address 0x00040000, size 262144 bytes, erase returns EXTMEM_OK (the measured duration was 0 ms). The subsequent write fails before any page-program command is sent: the driver’s initial WIP poll times out after 5 seconds.

FW erase begin idx=33 logical=0x00040000 cmd=0x00040000 size=262144
FW erase end idx=33 ... status=0 elapsed_ms=0

FW write begin idx=33 addr=0x00040000 ... bytes=262144
XSPI poll fail cmd=0x05 addr=0x00000000 timeout=5000
  match=0x00 mask=0x01 hal=3 err=0x00000001
  dr=0x00000041 im=1 am=0 dm=16777216
NOR WIP config cmd=0x05 addr=0x00 bit=0 polarity=0
FW write end idx=33 status=-3 elapsed_ms=5001

The poll expects status bit 0 to be zero, but the captured data register value is 0x41. I’m unsure whether the driver is using the correct status-read command, protocol, and WIP interpretation for this SEMPER device after initialization, or whether the erase command’s apparent success is misleading.

What is the recommended STM32 External Memory Manager/SFDP configuration and command sequence for polling WIP and programming this SEMPER flash in this XSPI mode? Is there a known limitation or required configuration for SEMPER status-register access or hybrid-sector erase/program operations?

I’m able to read the memory via Mapped Mode

[Huell]

Hello ​@nico23,

We encountered the same issue with the S28HS512T flash device. Unfortunately, the current version of the STM32 External Memory Manager does not appear to support this device correctly. In our case, initialization fails because status register read operations consistently time out.

We noticed that ST has introduced a Cypress/Infineon-specific workaround in SAL_XSPI_CheckStatusRegister(), which forces status register reads to use a single data line. However, this workaround does not seem to work correctly with the S28HS512T.

We also investigated the U-Boot implementation and identified several S28HS-specific fixes and workarounds that appear to be missing from ST's middleware:

https://github.com/u-boot/u-boot/blob/main/drivers/mtd/spi/spi-nor-core.c

Hopefully, ST will address these compatibility issues and introduce proper support for the S28HS flash family in a future release.
 

[nico23]

Thanks for pointing it out and for the GitHub link. I’m glad that I’m not the only one having issue with this specific chip.

Ultimately, have you been able to use the memory with the ST's middleware, maybe patching it following u-boot implementation, or did you had to write specific API to manage erase/write?

[Huell]

Unfortunately, we postponed implementing a patch based on the U-Boot implementation. For now, we replaced the S28HS512T with a pin-compatible flash supported by ST’s middleware, so we did not develop custom erase/write APIs.

[Fatih_Yildirim]

I am experiencing the same issue on the STM32H7S8L8. l am using STExternal MemManager and also encounter an error when reading the flash status register. Raising visibility on this Issue

[nico23]

yeah, I’m using the STM32H7S8L8 as well. The title is misleading :(