STM32 MCUs

Hello everyone,I am using STM32F103ZG MCU in a custom board for more than 7 years; 5 years ago, for shortage issues, I change the LSE oscillator from  MC-306 32.768K-E3 (CL=6pF; ESR=50k max) to 9HT10-32.768KAZY-T (CL=7pF; ESR=70k max) and I changed the external CL capacitance from 3.3pF to 10pF. I had no problems for 5 years. Now, in several boards, the LSE clock takes long time to start or even does not start until I “perturb the system” touching the capacitors or the uC’s pins with my finger.Looking at the uC’s datasheets it seems that the feedback resistor of the oscillator’s internal circuitry (don’t know if is a “real” resistor or an equivalent resistance given by the internal circuitry) is 5M but, with indirect measurement, it seems to be much more than 5M (like hundred times more). This is for both the old boards and the “faulty” new ones, so is not (perhaps) an issue caused by the productive process of the uC.As I written before some faulty boards in which the LSE at last start

Hello,I am currently working with the STM32N6 and debugging the boot sequence using the BootROM traces. I am dumping the secure and non-secure RAM ring buffers via STM32CubeProgrammer while the chip is in the Open state (using hotplug).To decode the traces, I am referring to the “official” ST template: Template_BootRom_traces/FSBL/Src/rom_trace_parser.c.However, I have noticed that the BootROM outputs several message IDs that are entirely missing from the switch statement in the romTrace_ParseRecord() function. Because these IDs are omitted from the table, they just get skipped by the C API, making it difficult to fully understand the boot execution flow.My questions are:  1. Is there an updated version of rom_trace_parser.c available that includes a more complete table of these message IDs?  2. Alternatively, is there a reference manual or document that lists all possible BootROM trace message codes and their meanings? Any pointers would be greatly appreciated.Thank you!

Hello.I’ve noticed a discrepancy in the documentation. The electrical schematics for the NUCLEO32 board show that D8 is connected to PF0/PC14 and that D7 is connected to PF1/PC15. However UM1956 User manual for STM32 Nucleo-32 boards (MB1180) says throughout the manual that D8 is connected to PF1/PC15 and that D7 is connected to PF0/PC14.

I have started a project in stm32g484. I have understood the concept of the HRTIM.i have reviewd the example projects also.I have a question regarding the Configuration of the HRTIM.I am not able to understand on what basis the Compare Unit1,Compare Unit 2,Compare Unit 3,Compare Unit 4 is being filled up.Can anyone please tell me.How to configure and on what basis we should fill the values? Is there any pdf related to the HRTIM configuration.

It seems odd that this semaphore doesn’t apply across the entire STM32WB family.   Is this really the case, and if so, why? 

Hello,I have two issues with the octospi controllers of the STM32L4P5.First issue.I can’t get both controller to work simultaneously.My target was to use one controller with a QSPI flash (W25Q512JVEIQ) and the second one with an APMemory QSPI PSRAM (APS6404L).I started the project by getting the code to work (it was a port from an STM32L496 project) for the flash.After some adjustments, the code works properly in quad spi mode.Then I added the second controller and doing that brokes the project.The second controller works, but the first one stopped working.I run some checks with a logic analyzer and found that ther is no signals on the I/O lines.CS# is HIGH and never goes low and there is no clock.CS# and clock are properly generated for the second controller.Second issueI can’t get the memory mapped mode to work.The mode is p^roperly enabled, I can read data from 0x90000000 without throwing a hard fault, but data is always 0.I’m wondering if this could be related to the flash model.It

I want to design my own UART and JTAG programming interface for the STM32C562RE controller, as well as for an external programming setup. However, I have not been able to find any relevant application notes or reference designs. Could you please help me with the required documentation or guidance?

Hello all, Im Currently working with my own Hardware with the L072CZTx on it.I want to use a Terminal over the 2 USB Pins.(USB_DP and USB_DM)I activated the Clocks with 48MHzActivated USBActivated USB_ Device as a Communication Device Class(Virtual Port COM) I got told i should see it in the Device Manager as a Com Port or a unidentified Device.Sadly i can only see my V3set im using to Programm the Controller with (SWD). If very new to Programming with STM32 and if you have any ideas that could fix it i would really appreciate it. Thank you in Advance

I am using Azure RTOS NetX Secure / NetX Duo on an STM32U585 for TLS client communication and would like clarification regarding certificate chain verification.I have the following scenario:The TLS server sends a valid server certificate. The server also sends an expired intermediate CA certificate as part of the certificate chain. The client has a valid copy of the same intermediate CA certificate stored locally and added using nx_secure_tls_local_certificate_add(). The trusted root CA is also configured in the TLS trusted certificate store.During debugging, I observed the following:_nx_secure_tls_process_remote_certificate() correctly parses the certificates received from the server. Wireshark also confirms that the server is sending the expired intermediate certificate. _nx_secure_x509_remote_endpoint_certificate_get() correctly identifies the remote endpoint certificate. During _nx_secure_x509_certificate_chain_verify(), NetX calls:_nx_secure_x509_store_certificate_find() to locate

Hello everyone,I am currently working on a project on STM32F756 with SAI1A as asynchronous master and SAI2B as synchronous slave.Config :TDM Mode frame length 256, data size 32, slots 8 Freq 96k Fifo threshold full Master ext sync out enable Slave sync with SAI1Then in my code I call HAL_SAI_Transmit_DMA for Slave then for Master but the Slave sends its data 5 us before the master because BCLK and FS clocks are always active.So the Slave does not wait for the master to have its buffer ready. They should be synchro with this config right ? Is there a way to have perfect sync between both SAIs ? Thanks

Hi everyone,I am working on a project using the STM32WB55RG and would appreciate some guidance on integrating the STM32WB BLE stack into an existing FreeRTOS-based application.Current SetupMy project currently uses:MCU: STM32WB55RG RTOS: FreeRTOS with the CMSIS-RTOS2 API Configuration/code generation: STM32CubeMX An existing firmware application that is already functional and uses multiple FreeRTOS tasks, semaphores, flags, etc.At this stage of the project, changing to another RTOS or converting the application to bare-metal is unfortunately not an option, so I need to integrate BLE into the existing FreeRTOS/CMSIS-RTOS2 architecture.BLE RequirementsI would like the STM32WB55 to support:BLE advertising Another BLE device should be able to connect to the STM32WB55 and retrieve data from it, most likely through a custom GATT service/characteristic.ProblemI enabled BLE using STM32CubeMX and generated the required BLE code.However, I am having problems when initializing the BLE application

Hi,I’m trying to run a simple FSBL application from NOR flash on a custom STM32N657L0 board. The application runs without any issues in Dev-Mode from RAM. However, when I sign and flash the same application, it does not run.I’m using a custom external flash loader for the W25Q64JV NOR flash, based on the template provided in the STM32Cube repository. I’ve attached it for your reference.I also have a question regarding VDDCORE. It is currently set to 0.89 V, while we are operating in normal-speed mode. Should we reduce the voltage to 0.8 V? Could the current VDDCORE setting be a potential cause of the problem?General info:Board is working with 3v3 domain XSPI2 is used. HSE with no PLL is used (48MHz).I have used the following the guides provided by ST for the tests:   

I have been chasing a very intermitant issue with some STM32L100 based products.The problem shows itself with the MCU being reset by the WDT part way through the initialisation sequence.This issue only displays itself when the MCU has reset itself using  NVIC_SystemReset();E.G. the program flow is as followsRunning programNVIC_SystemReset(); is calledMCU resets and goes through the init section in main.cpart way through the init section, it locks up and the wdt resets the mcu. Once it has started to do this, it can stay in this reboot loop until you re-power the MCU OR it can recover after only one reboot. There is no pattern to how it recovers without a power cycleThis does not happen when you power up the mcu, it only happens when the mcu has been reset using NVIC_SystemReset();Plugging in a USB cable into the board and a pc stops the reboot cycle. (no app on the pc needs to be using the usb com port) We have several thousand products in the field and we come across this issue once e

Hello everyone , I was reading in the power controller section 5 in RM0368 , I had some difficulties understanding some terms and distinctions and I would like your support please . The main goal ifor me is to  categorize each group of functionalities by their power source as as being Digital VDD , Analog VDDA , VBAT powered . According to figure 7 page 71 :  The analog domain is ADC , RCs and PLLs and .. etc , I would like to know a complete list of the rest of functionalities associated with the analog Domain , Even in DS9716 Page 18 section 3.13 third Bullet it specify a partial list of blocks but it includes “Reset Blocks”  , what does reset block refer to exactly can i conclude safely its the POR , PDR , BOR , PVD blocks exactly or that is not correct or partial .Regarding digital domain the word “digital” does it mean “Digital peripherals” ?  Why “IO Logic” different  from “GPIO peripheral” being a part of digital peripherals ?For VBAT , what is the functionality of “wakeup logic

Title: Hello,I am investigating BootROM behavior on an STM32N6570-DK.My expectation is based on the STM32N6 BootROM documentation and errata:- PG10 is used as BootFailedn in blocking failure conditions.<sup class="chatgpt-doc-sup"><span title="ES0620-STM32N6_Rev4.pdf, page 7" /></sup>- There is a known erratum: “PG10 (BootFailedn) signal not maintained at 1 during blocking failure”, with no workaround listed.<sup class="chatgpt-doc-sup"><span title="ES0620-STM32N6_Rev4.pdf, page 7" /></sup>Observed behavior on my board:- If the content of the OctaFlash is erased, I do not receive the expected serial BootFail-related output on PG10 / USART5_TX.- Measuring PG10 with an oscilloscope, I see a ~4.3 MHz square wave instead.- I observe the same square wave again after setting BOOT1=1 and BOOT0=0 and then resetting the board.Additional context:- I found guidance that Development Boot mode can be relevant for programming/erasing external flash on STM32N6570-D

Hi,I have custom PCB with STM32WB5MMG, which has STM32WB55VGY. I want to update FUS and software stuck and I would like to confirm which start address is the correct one. Should it be the one from the column STM32WB5xxG(1M) (as the chip is STM32WB5MMG) or the one from column STM32WB5xxY(640k) (as the MCU is STM32WB55VGY)?  

Hello everyone,I am trying to use TLS 1.3 with Mbed TLS on an STM32H573 through the Secure Manager’s Global PSA API.At the moment, I am seeing the following errors: psa_sign_hash() / psa_sign_message()→ PSA_ERROR_NOT_PERMITTEDpsa_generate_key() / psa_import_key()→ PSA_ERROR_GENERIC_ERRORThe persistent ECC keys are provisioned with the required signing permissions, and both the Secure Manager and the non-secure application start correctly.Some TLS 1.3 HKDF operations had to be implemented locally because the PSA Crypto API version in use is 1.0 and does not provide separate HKDF-Extract and HKDF-Expand algorithms.My questions are:Are persistent ECC keys supported with psa_sign_hash() through the Global PSA API? Does the Secure Manager support volatile keys with psa_generate_key() and psa_import_key()? Are additional permissions or a Secure Module required? Is there a support matrix or an official TLS 1.3 example for this setup? Does anyone have experience with Secure Manager and MbedTLS

Hi,We are currently using the STM32H563ZIT6 microcontroller in our project. We would like to obtain the FIT (Failure In Time) / reliability data for this device for our reliability and FMECA analysis.Please share the latest available reliability data or the relevant ST document/reference.Thank you for your support.Best regards,Geetha Thota.

Hello everyone.My fight with STM32H7R7 continues.I'm trying to get the simplest example of triggering the EXTI interrupt on an STM32H7R7I8T6. I've run this thousands of times on other H7 series MCUs and never had any problems. I have a button and an LED connected to the MCU as shown in the diagram.Pin PC11 configured as below:/*Configure GPIO pin : PC11 */GPIO_InitStruct.Pin = GPIO_PIN_11;GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;GPIO_InitStruct.Pull = GPIO_NOPULL;HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);/* EXTI interrupt init*/HAL_NVIC_SetPriority(EXTI11_IRQn, 0, 0);HAL_NVIC_EnableIRQ(EXTI11_IRQn); I added to the Callback code as always:/* USER CODE BEGIN 4 */void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin){    if(GPIO_Pin == GPIO_PIN_11)    {        HAL_GPIO_TogglePin(GPIOA, GPIO_PIN_12);    }}/* USER CODE END 4 */ Optionally, I also added lines in the Callback itself:/* USER CODE BEGIN 4 */void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin){ if(GPIO_Pin == GPIO_PIN_11) { HAL_GPIO_Togg

Hi guys,  This is my first topic and I hope this is the right section.I’m trying to connect the EVLSPIN32G0B2 evaluation board to the ST.LINK/V2 program tool connected to PC via USB.When I click on Connect on the STM32CubeProgrammer I get the error “ST-LINK error (DEV_CONNECT_ERR)”. Of course, when I do this I have the evaluation board connected to another usb port in order to supply the micro. Why doesn’t it works? I can’t find my error. I have another question: which is the program to be loaded on the EVLSPIN32G0B2 to make it working with Motor Pilor and be able to configure my brushless motor ? Thank youStefano EDIT:I didn’t mentioned that the ST-LINK is connected to the EVLSPIN32G0B2 via a cable coded ARM-JTAB-20-10 bought on Mouser Electronic’s site and it is connected to the RESERVED connector on the EVLSPIN32G0B2 board.

Hello ST Community,I am attempting to run the LoRaWAN_End_Node_LBM example project from the STM32CubeWL MCU Firmware Package on a NUCLEO-WL55JC1 board, connecting to a ChirpStack LoRaWAN Network Server.While ChirpStack shows both the Join Request and Join Accept frames, the node fails to join and loops endlessly in a join retry state.Configuration & Keys    Updated AppEUI in se-identity.h to match ChirpStack settings.    Tested on STM32CubeWL Firmware Package V1.6.0 (and verified same issue on V1.5.0).Environment / Software Versions    Application: LoRaWAN_End_Node_LBM (V1.6.0)    Middleware (MW) LoRaWAN: V1.1.0    Middleware (MW) Radio: V1.4.0    L2 Spec: V1.0.4    RP Spec: V2-1.0.4Serial Monitor188s692: TX DONE188s739: RX1 LoRa at 4953 ms freq:868300000, DR 4, BW125, rx timeout 16 ms193s827: RX DONE193s827: RP: RX size 33193s828: Process join accept failed with code = 14193s828:Receive a bad packet on RX1 for stack_id = 0 continue with RX2193s828: RX2 LoRa at 895 ms freq:86952500

I’m just starting a new project using the STM32H563. It has 16 channels of DMA, 8 in GPDMA1 and 8 in GPDMA2. I have at least 11 peripherals I’d like to use DMA for, UARTs, I2C and CAN. That means 22 channels of DMA if I want to use DMA for RX and TX. Does it make sense, or will it even work to use DMA for the RX side of a UART (for example) and IT for the TX side?My goal is to eliminate or at least minimize blocking in my program. I care more about DMA on the RX side since I often don’t know how many bytes will be in the message from the peripheral. I’ve used character match on the STM32H7A3 to deal with that in the past and the H563 is supposed to support character match also. TX is easier since I always know how many bytes I’m sending. I understand I’m still using CPU cycles to TX in IT mode but I don’t think that will cause any significant issues (I hope).

Dear ST Team,I have a STEVAL-ESC002V1 board and tried to generate the source code using MC Workbench, but I could not find the STEVAL-ESC002V1 board in the available options.I also checked the ST website and found firmware support for the IAR IDE:https://www.st.com/en/embedded-software/stsw-esc002v1.htmlHowever, I need support for STM32CubeIDE.Could you please confirm if STM32CubeIDE support is available for the STEVAL-ESC002V1 and guide me on how to generate or obtain the source code for this board?Thanks & Regards,Prashant Gautam

Hello everyone,I need to design a board featuring two STM32 microcontrollers that must operate in sync. To ensure clock synchronization, I plan to use a single external crystal.My proposed hardware approach is: Connect the standard external crystal (HSE) to MCU 1. Route the MCO (Microcontroller Clock Output) pin of MCU 1 to the OSC_IN pin of MCU 2. Configure MCU 2 to use HSE Bypass Mode, leaving its OSC_OUT pin floating. Place a series damping resistor on the trace between MCO and OSC_IN to prevent ringing. Could you please confirm if this topology is the correct and officially recommended approach for STM32 devices? Thanks in advance for your time and suggestions!

Hello Everyone,I am aiming to integrate a 64mb NOR Flash non-volatile memory to my stm32n6,However, the recommended models were MX66UW1G45GXDI00 and MX25UM51245GXDI00,They are out of stock on every major electronics market in the world,,are there any legit alternatives to these models , that are compaitable with stm32n6 and serves my need,If so please let me know.Thanking you