STM32 MCUs

STM32G4 Reference Manual (RM0440) states that all of the Timer x counter enable (in HRTIM_MCR) bits “must not be changed within a minimum of 8 cycles of fHRTIM clock.” What does that mean? How can I ever set or reset them when fHRTIM is the same as my processor core clock?  

Regarding the methods for reading data from the ADC injected group, I’ve only seen two approaches: interrupts and polling. Can I directly map memory in the software to ADCx->JDR1 to retrieve the data?  Just like：#define ADC_ADCRESULT0_ADDR ((volatile uint32_t*)&ADC1->JDR1)inline static const *uint32_t adc_buffer[0] = {ADC_ADCRESULT0_ADDR }

I have one question.The L451CC has 160K of SRAM split in 128K + 64K.According to the datasheet SRAM2 is rermapped just on top of SRAM1 giving a full block of 160K.Wonderful, but… not so wonderful because CubeIDE ignores the SRAM2 and restrict the memory space to SRAM1.Is there a way to use SRAM2 E.G. by writing a customized malloc like function (I did that for the L429 series and it works fine) ?static volatile void * ccm_current_pointer;static volatile uint32_t ccm_current_free_memory;static void ccm_Malloc_failed(void);// ADJUST ONLY THE RESERVED AREA SIZE// TO CHANGE THE CCM HEAP SIZE#define CCM_RESERVED_SIZE 0#define CCM_AS_HEAP_SIZE 65536 - CCM_RESERVED_SIZE#define CCM_AS_HEAP_BASE (0x10000000 + CCM_RESERVED_SIZE)void ccm_Heap_init(void){ ccm_current_pointer = (void *) CCM_AS_HEAP_BASE; ccm_current_free_memory = CCM_AS_HEAP_SIZE; memset((void *) ccm_current_pointer, 0, ccm_current_free_memory);}void * ccm_Malloc(uint32_t block_size, bool force_in_sram){ void * _ptr; uint32_t _

Hello, I am currently performing an ISO 13849-1 assessment and creating a SISTEMA model for a chemical dosing system.The safety-related control architecture includes a STM32F767BI. I have reviewed:- STM32F767 datasheet- STM32F7 Safety Manual (UM2318)- STM32F7 self-test library documentation The Safety Manual references:- AN5132 (FMEDA results)- AN5137 (FMEA results) However, these documents do not appear to be publicly available. I am looking for guidance on the following: 1. Is there an official FIT value, failure rate, PFHd or MTTFd available for the STM32F767 family?2. Are AN5132 and AN5137 available through ST support or under NDA? Thank you.

I purchased the EVLGANSPIN2-3PH evaluation module. I added a definition for this module in the MCSDK. I connected a BLDC motor from a well-known drill operating at a nominal voltage of 230VAC to it. I measured the resistance and inductance of the windings, as well as the number of poles. The code was generated in MCSDK v. 6.4.2 in FOC mode with the profiling option – it can only be generated in STO-PLL mode, so the HALL sensors are not used. The PWM frequency is 10 kHz, and the overcurrent control option is enabled.I started all tests at 70 VDC with a limit of 800 mA.After starting the profiler, the motor hums quietly for a moment, and profiling freezes at about 30%. I can't get the profiler to work properly.I started the MotorPilot, and the motor only squealed. Current consumption is about 250 mA.Redesigning the project to STO-Cordic mode allowed the motor to start in MotorPilot. It starts slowly but smoothly and gains speed. The current draw also increases until it reaches the power

Hi everyone,I am currently testing the Current Regulator Step Response as described in the ST Motor Control documentation.I do get the sharp edges, but I see short peaks/overshoot in the current waveform.  Setup: Custom Board → EVSPIN32G4 has been taken as reference Step‑test configured exactly as in the document 3‑shunt topology PWM frequency: 20 kHz BLDC Motor  Motor Control Part3 - Troubleshooting and fine tuning_v2.pdf - Google Drive  What could be the reason for the peaks?  

I configured usb cdc class with freertos using cubemx and generated the code and tried to run it and when i checked the windows device manager, i was unable to see the usb virtual com port, board i am using is stm32h735-g DK. The clock and pin configurations are all correct. please help me out, attached the ioc file in the forum. 

STM32N6: Black screen after HAL_NVIC_SystemReset() — FSBL not booting, works fine after NRST/power cycleGövde:Hello,I have a bootloader (FSBL) and a separate application on anSTM32N645L0, running from external XSPI NOR flash MX25UM25645GXDI00 in memory-mapped XIP mode (Octal DTR).Setup:FSBL configures the external flash into Octal DTR mode (volatile CR) at every boot and shows update/bootloader graphics on the display The application runs its own graphics To enter bootloader mode from the application, call HAL_NVIC_SystemReset()Problem:After HAL_NVIC_SystemReset(), the device stays on a black screen — the FSBL graphics never appear. However, if I reset via the NRST button or a full power cycle, everything boots normally.What I suspect:Since the N6 is flashless, BootROM must read the FSBL from external flash in standard SPI mode. My theory is that after a software reset the flash chip stays in Octal DTR mode (it doesn't lose power), so BootROM cannot read the FSBL at all.Questions:Is th

HiI just noticed an error in the STM32WB5MM-DK User Manual V5 UM2825:In “Table 19. ARDUINO® connector pinout” there is the signal PE3 at pin 5 of the CN4 connector.The EXTI3_IRQHandler of my project and the Board Schematic V2 MB1292-D01 say otherwise: Its actually PE4.Just letting you know. I was not sure where to input this information and chose to open this thread to have it placed.Maybe someone else might save some time by finding this.Best regardsManuel

I'm developing with an STM32WBA2.I want to communicate via Bluetooth every 10ms, but where in the source code should I modify the default connection interval?I couldn't find a relevant item in CubeMX's STM32_WPAN.

Hello,I implement kind of “lazy write cache” for flash and have problem.The consumer thread sends out cache write requests to the flash thread using events.The flash thread starts a SW timer which fires an event if no more cache write occurs.In the oscilloscope I see that the timer callback is run after timeout occured but the flash thread, which is triggered by the callback, is not executed immediately (it is run as soon as the next cache write event is received).I’m afraid this is a priority problem, but fiddling with task prios doesn’t help.Any idea is greatly appreciated!Thanks, Jochenuint32_t NCB_Cache_Write(eREQID_t eRid, ePNORNUM_t eFid, uint32_t ulOfs, uint8_t bData) { psNcbTaskArgs_t psArgs = &asNcbTaskArgs[eFid]; psArgs->pusBuf[ulOfs] = bData; psArgs->ulAdr = ulOfs; // run core thread after send request called by upper layer / send notification osEventFlagsSet(psArgs->phEventId, NCB_FLAG_FLUSH_REQ);}static void NCB_Timer_CB(void *arg) { // set TIMER event flag of

Hi there, I am after some advice on the best way to implement an FOC BLDC controller on an STM32H725RGV3 based board. I’ve inherited this board and as a result am not able to choose the microcontroller that exists on it. If it were up to me, I would’ve chosen a device from the STM32G4 range. Regardless, I ideally would like to use X-CUBE-MCSDK so I am not re-inventing the wheel, however, the closest boards are the NUCLEO-H745/55ZI-Q which is a dual core stm32h7 based board.Current reading topology: Three Shunt Resistors Control schemes required: FOC (torque control), speed and position control with absolute encoder.Comms interface: CANBus (expect to implement business logic myself)Modulation technique: Ideally SVPWM (is this the default)Motor: CustomWhat is the prescribed workflow for this application? Should I create a board based on the NUCLEO-H745/55ZI-Q and then attempt to modify the IOC to match my board? I was considering trying to use the example project “FOC STM32H745ZI with IH

Hi,I have been using a NUCLEO-H7A3ZI-Q board in a research project for a magnetic spectrometer. The input the the Nucleo board is two short pulses which I have for a year or so, been using to generate trigger pulses using the INP inputs of  COMP1 and COMP2 with INN connected to DAC1_OUT1 and DAC2_OUT2, respectively by on-chip connection. The external outputs of COMP1 and COMP2 drive TIM1 and TIM3 that trigger ADC1 and ADC2.  I used STMCubeMX 6.17.0 and STMCubeIDE 2.1.0 for authoring the code.  I I needed to recompile a new version and I experienced that the output from COMP1 was not working with random fluctuations between 0 and 1. Previously, the COMP1 output was sharp pulse with a duration the input pulse was over the threshold set by DAC1_OUT1. The COMP2 output behaves as it should. I tried to check the output of DAC1_OUT1 and DAC1_OUT2. Only the latter could be directed to an external pin and this worked as intended and produced the signals as expected. DAC_1_OUT1 was restricted to

Our team is looking to implement an application based on the upstream Trusted Firmware M (TF-M) framework (https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/) to take advantage of the latest security capabilities provided by the framework.    But we’ve found that with the latest TF-M LTS release, 2.3.x, support for the HW cryptographic acceleration peripherals of the STM32U5 has been removed, due to the migration from mbedTLS to TF-PSA-crypto library.Are there any plans for STM to implement support for crypto HW acceleration for STM32U5 in TF-PSA-crypto and TF-M 2.3.x?

I am working with the STM32U5G9J-DK2 Discovery kit and trying to use the USBX CDC_ACM device example. The available project description says this example demonstrates an Azure RTOS USBX USB device communication class (CDC_ACM) application that emulates a USB-to-UART bridge and provides the required device and class descriptors for a compliant USB CDC_ACM device.According to the example description, the application creates three threads: one to initialize the USB OTG HAL PCD driver and start the device, one to read data from the virtual COM port, and one to send received data over UART. The same description also says that the USB device start/stop is controlled through messages coming from the USB_PD interface when the board is plugged into or unplugged from the host PC.I would like to confirm the correct hardware connection and board configuration for this use case, because the kit also includes an STLINK-V3EC with its own USB Virtual COM port bridge. The documentation states that the

We need to use an ST67W611M1 on an STM32H5, running the Zephyr operating system in softAP mode. Currently, the Zephyr driver for the ST67W611M1 only supports STA mode. Is there a roadmap for this feature?Thanks,Denis M.

I am using the EEPROM emulation (X-CUBE-EEPROM) on a STM32C0.The default setting for number of variables is 100 : In eeprom_emul_conf.h : #define NB_OF_VARIABLES 100U /*!< Number of variables to handle in eeprom */If I understand this emulation correctly, it uses a number of 2K flash pages (minimum 2 for alternating...).Also, each (32bit) variable is stored as 8 bytes : 16bit virtual address, 32bit data, 16bit CRC.I understood there is also some header overhead of 32 bytes per 2K page.So the number of variables fitting in a single page is (2048 - 32) / 8 = 252So my question is then : why is the default value set to 100 io. 252 ???

Hi!SetupMCU: STM32H573 (Cortex-M33, TrustZone enabled) Secure world: STM32 Secure Manager via SMAK, product state CLOSED Non-secure app: CycloneTCP / CycloneSSL / CycloneCRYPTO (Oryx Embedded) Use case: HTTPS server on a networked device with a long-lived device identity key that must never leave the secure world, plus automated certificate renewal (EST/ACME)What I understand so far!!!mbedTLS consumes the PSA Crypto API natively (MBEDTLS_USE_PSA_CRYPTO plus mbedtls_pk_setup_opaque()), and wolfSSL has partial PSA support via WOLFSSL_HAVE_PSA. Both therefore let the private key stay inside Secure Manager while the non-secure application holds only a psa_key_id_t handle.CycloneCRYPTO has no PSA backend as far as I can tell. Instead it ships register-level STM32H5 ports (stm32h5xx_crypto_pkc.c, stm32h5xx_crypto_cipher.c, stm32h5xx_crypto_hash.c, stm32h5xx_crypto_trng.c) that drive PKA, AES/SAES, HASH and RNG directly. That looks like a direct conflict with Secure Manager, which claims seve

Hi,I need an ST-Link to debug external STM32U0 devices, specifically to modify option bytes and use RDP regression with OEM keys via STM32CubeProgrammer, and I was wondering if the JP6-11 pins on the Nucleo-U083RC could be connected to another MCU to use it as an ST-Link. Thanks in advance 

Hello,I need very low latency, short distance, robust proprietary RF connection with encryption. Drone will not have much complicated functions, just will fly, make flip, hover etc. like other toy drones. For lowest latency, as far as I understand, I need lowest level hardware access. All three of STM32WBA, STM32WB and STM32WB0 are doing it via different ways but which one is better for me, I don’t know. STM32WB looks sensible because it has 2 cores to seperate RF functions for faster responses but it is not one of the latest generations and not sure whether it worth to learn. Which series is the most suitable for such project you think? Thanks for all responses.

For STM32U575/U585, the STM32U5 Customer Webinar says that the 256-bit BHK is “Generated by the secure boot code”. Is the intended implementation to generate 256 bits from the STM32 RNG when the BHK backup registers are uninitialized, or should secure boot restore/derive BHK from a persistent OEM-provisioned secret? Is there ST reference source code implementing the generation, TAMP_BKP[7:0]R write, and BHKLOCK sequence?

Good morning,  I’m trying to build a project based on EVLSPIN32G0B2 evaluation board.I’m trying to establish a connection between the board and the STM32CubeProgrammer.Checking the electrical scheme, I saw that the USB connector on the evaluation board is connected to the port PB6 and PB7 (pins 45 and 46 of the SPIN32G0B2) which are the wires of an I2C port. Do I need any interface ?What’s the secret for a working connections ? ThanksStefano P.S. there’s another post on the same argument I wrote few days ago.I can’t delete it, can a moderator delete it for me ? It is useless. Thanks. 

I am trying to jump from bootloader to application at address 0x08004800 i STM32G070 but it crashes.The same code worked fine jumping to address  0x08007000Bootloader jump looks like this:#define BL_FLASH_START 0x08000000#define BL_FLASH_SIZE 0x4800 // 18 kB reserverade för BL, OBS! Startadress måste vara alignad mot 32 byte, dvs jämnt delbar med 32..#define BL_FLASH_END (BL_FLASH_START + BL_FLASH_SIZE-4) // 4 byte checksumma#define APP_FLASH_BANK_SIZE 0xDC00 // 55 kB / appl bank// Defines för applikationen#define FLASH_START (BL_FLASH_START + BL_FLASH_SIZE)....HW_WD_Trig();JumpAddress = *(uint32_t*) (FLASH_START + 4);Jump_To_Application = (pFunction) JumpAddress;// disable global interrupt__disable_irq();JumpAddress = *(uint32_t*) (FLASH_START + 4);Jump_To_Application = (pFunction) JumpAddress;/* Initialize user application's Stack Pointer */__set_MSP(*(uint32_t*) (FLASH_START));Jump_To_Application(); .ld for bor bootloader looks like:/* Entry Point */ENTRY(Reset_Handler)/* Highest ad

Hi all:I have a number of firmwares which use the older Standard Peripheral Library for STM32F4xx etc.I could switch to the new Low-Layer drivers, but I doubt it is worth the effort.I actually found the old Standard Peripheral Libraries quite all right. Unfortunately, STM is not maintaining them anymore, even in the face of obvious bugs like this one:Standard Peripheral Library limits STM32F4xx USART to 7.5 Mbit/s, instead of max 10.5 Mbit/shttps://community.st.com/stm32-mcus-products-25/standard-peripheral-library-limits-stm32f4xx-usart-to-7-5-mbit-s-instead-of-max-10-5-mbit-s-82037Are there any community forks of the Standard Peripheral Libraries I could switch to?Thanks in advance,  rdiez

Dear ST Community,We are working on a custom board using the STM32H747XG controller with a MIPI DSI display interface.Our display panel is RK055MHD091A0-CTG, with a resolution of 720 × 1280. The display uses the HX8394-F TFT driver IC, and we are using the 2-lane MIPI DSI interface: DSI Data Lane 0 DSI Data Lane 1 DSI Clock Lane We have configured the STM32H747 DSI Host in Video Mode and are using LTDC with an SDRAM framebuffer.The HX8394-F supports DBI Type C option 1, 3-wire serial bus to access command set under DSI I/F. The 3-wire serial bus is use: chip select line (CSX), serial input data (SDI),serial output data (SDO) and serial transfer clock line (SCL).According to the HX8394-F display driver requirements, the panel requires an initialization sequence with several commands for configuring parameters such as power, MIPI settings, gamma, GIP, etc., before starting the display.We would like guidance on the correct way to send these HX8394-F initialization commands from the ST