I2c SCLDEL and SDADEL settings

[GanZ]

I am using STM32CubeMx to calculate the i2C timing for i2C master. The i2C kernel clock is 200MHz. I2C speed frequency is 400KHz. Coefficient of digital filter 0, Analog Filter Enabled.

 

If Rise time and Fall time were set to 0,  TimingR = 0x109035B7. With this setting, Tpresc = 10ns, Tsclh = 1840ns,  Tscll = 540ns, Tscldel = 100ns, Tsdadel = 10ns, Tsclh + Tscll + Tscldel +Tsdadel = 2490ns. Actual SCL clock is measured ~2500ns.

 

If Rise time and Fall time are set to 300ns( I2C Fast mode max tr and tf),  TimingR = 0x40FA1531. With this setting, Tpresc = 25ns, Tsclh = 1250ns,  Tscll = 550ns, T​​​​​​​scldel = 400ns, Tsdadel = 275ns, Tsclh + Tscll + Tscldel +Tsdadel = 2475ns. Actual SCL clock period is measured only ~2000ns (Tsclh ~650ns, Tscll ~1350ns).

Why is SCL clock period too low in the latter case? Should SCL be stretching low for Tscldel +Tsdadel?

[AScha.3]

You are playing around in the depths of the mystical calculations of the MX software.

Basically all these rise and fall time values change nothing on the signal at all.

All that's changed in the end is the moment of sampling, the decision , is it lo or hi.

And if you want to modify it , read the register description in rm and set all values yourself.

In general better just leave these rise and fall time values at its starting values , then the timing is basically correct.

And set the analog and digital filters, to suppress any spurious spikes, that would spoil the I2C function.

Most important is a good hardware design, short lines, good ground, no spikes induced, matching pullups.

Because any “timing” setting will not help, if you have a spike on the I2C signal, then the I2C might hang up and you never get it back to working , until reset or power cycle.