STM32G431: HSI16 — are fHSI16 (@30 °C) and Δtemp(HSI16) additive? (DS12589 Rev 2, Table 44)
Hi,
I am using STM32G431CBU6 with HSI16 as the only clock source (no external crystal on the board), and I need to budget the resulting frequency error. I have a few questions about DS12589 Rev 2 (October 2019), Table 44 "HSI16 oscillator characteristics", page 107, and Figure 23 on the same page.
Q1 (main question) — Are fHSI16 and Δtemp(HSI16) additive, or is Δtemp inclusive?
Table 44 lists two separate parameters:
| Symbol | Conditions | Min | Max |
|---|---|---|---|
| fHSI16 | VDD = 3.0 V, TA = 30 °C | 15.88 MHz | 16.08 MHz |
| Δtemp(HSI16) | TA = 0 to 85 °C | −1 % | +1 % |
For a single device over the 0 to 85 °C range, is the worst-case total frequency error:
- (a) −7500 ppm − 10000 ppm = −17500 ppm … +5000 ppm + 10000 ppm = +15000 ppm (i.e. the two parameters add), or
- (b) ±10000 ppm (i.e. Δtemp already includes the initial tolerance at 30 °C)?
This makes a large practical difference for bit-timing budgets, so I would like to be sure.
Q2 — Is a typical temperature coefficient (ppm/°C) available?
Figure 23 shows mean/min/max curves, but Table 44 contains no ppm/°C entry. Is a typical temperature coefficient available for the 25–50 °C region, or numerical data behind Figure 23?
For reference, I measured +26.3 ppm/°C on one device (43 samples over 7.35 h, die temperature range 4.5 °C, regression not statistically significant, r² = 0.03), so I cannot tell from my own data whether that is representative.
Q3 — Factory calibration conditions and part-to-part spread
Table 44 gives fHSI16 at VDD = 3.0 V, TA = 30 °C.
- Is the factory trim performed at 30 °C?
- Is the factory HSITRIM reset value per-die, or a fixed constant?
- Note (1) says "Guaranteed by characterization results" — does that mean fHSI16 is not tested per part in production?
I measured four devices at the default (reset) HSITRIM, at room temperature (22 °C), each the mean of 5 × 30 s windows: +2616, +832, −256, +1606 ppm (span ≈ 2870 ppm). All are inside the −7500/+5000 ppm window, but I would like to know whether that spread is expected.
Q4 — Is the HSITRIM step size temperature-independent?
Table 44 gives TRIM (HSI16 user trimming step) as 0.2 / 0.3 / 0.4 % when the trimming code is not a multiple of 64, and −4 / −6 / −8 % when the code is a multiple of 64.
- Is the step size constant over −40 to 125 °C? (i.e. does a trim performed at room temperature stay valid over the full range?)
- I measured the step from HSITRIM = 64 to 63 as −3093 ppm (≈ −0.31 %), which matches the "not a multiple of 64" row — but 64 is a multiple of 64, where the table says −4 to −8 %. Could you clarify how these two rows should be read?
Q5 (minor) — Does Figure 23 include VDD variation?
ΔVDD(HSI16) is listed separately as −0.1 / +0.05 %. Are the Figure 23 min/max envelopes taken at a fixed VDD = 3.0 V, or do they already include VDD variation?
Measurement method used above, in case it matters: the MCU's microsecond timestamp counter is derived from the same PLL branch as the peripheral I am timing; I compare "microseconds counted by the device" against "wall-clock seconds elapsed on the host" across a 30 s window. Single-point uncertainty is ±16 ppm (round-trip jitter / window length). Repeat-to-repeat scatter of the same device at 30 s intervals is ≈51 ppm, growing to ≈184 ppm at 10 min intervals, so the device's own short-term wander dominates over the measurement uncertainty.
Thanks!
