STM32H755 DMA peripheral read timing differs from AN4031, actual hold time shorter, seeking explanation
Hello,
I have recently tested the timing of DMA reading data from GPIO on an STM32H755 and found that the required input signal hold time is shorter than what is described in AN4031. I would like to ask whether my understanding is incorrect or if it is due to architectural differences in the chip.
Test platform and configuration:
Hardware: NUCLEO-H755ZI-Q, using the CM4 core, CM7 idle.
System clock: SYSCLK = HCLK = PCLK2 = 8 MHz, APB2 timer clock = 8 MHz.
Timer: TIM1 configured in PWM mode, CH1 outputs a 1 MHz square wave with 50% duty cycle, and the DMA request for the CC1 event is enabled.
DMA: Using DMA1_Stream0, peripheral address is GPIOA->IDR, data width half-word (16 bits), peripheral address not incremented; memory address points to an SRAM array, half-word width, address incremented. FIFO disabled.
External signal: A signal generator produces a 1 MHz PWM signal connected to PA0, and the phase is adjusted so that its edges align with the edges of the TIM1_CH1 output.
Test method:
Start DMA, transfer 100 data items, then stop; discard the first 20 samples and observe the value of Bit0 in the remaining 80 data items.
Gradually adjust the external signal duty cycle (starting from 50% and increasing), and record the critical condition at which DMA correctly reads high/low levels.
At the same time, change the duty cycle of the TIM1_CH1 output to verify how long the external signal must remain stable relative to the CC1 event.
Observation:
When the external signal duty cycle exceeds 75%, the value of Bit0 read by DMA becomes stable at the expected level; if the TIM1_CH1 output duty cycle is adjusted to 25%, the critical point appears at 50%. This means that the external signal must remain stable for about 250 ns (25% of the 1 MHz period) after the CC1 event in order to be correctly latched by DMA.
However, AN4031 mentions that the peripheral port access/transfer time is at least 4 AHB cycles (which would be 500 ns here). Why is the observed hold time shorter? My guesses are:
-
The non-incrementing peripheral address causes the peripheral address computation phase (t_PAC) to be simplified or omitted;
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During continuous burst transfers, the peripheral port arbitration (t_PA) is not performed again;
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Or the DMA latches the peripheral data before the bus matrix arbitration (t_BMA).
Are these guesses valid? Or is the timing of the H7 series DMA fundamentally different from what is described in AN4031? I look forward to your reply. Thank you!
