LSE clock not starting correctly on STM32F103

[FrancescoV]

Hello everyone,

I am using STM32F103ZG MCU in a custom board for more than 7 years; 5 years ago, for shortage issues, I change the LSE oscillator from  MC-306 32.768K-E3 (CL=6pF; ESR=50k max) to 9HT10-32.768KAZY-T (CL=7pF; ESR=70k max) and I changed the external CL capacitance from 3.3pF to 10pF. I had no problems for 5 years. Now, in several boards, the LSE clock takes long time to start or even does not start until I “perturb the system” touching the capacitors or the uC’s pins with my finger.

Looking at the uC’s datasheets it seems that the feedback resistor of the oscillator’s internal circuitry (don’t know if is a “real” resistor or an equivalent resistance given by the internal circuitry) is 5M but, with indirect measurement, it seems to be much more than 5M (like hundred times more). This is for both the old boards and the “faulty” new ones, so is not (perhaps) an issue caused by the productive process of the uC.

As I written before some faulty boards in which the LSE at last starts may or may not start again once the uC is powered off and the backup battery is not supplying the backup circuitry, so the issue is not repeatable.

Using an external 10M resistor between LSE OSC_IN and OSC_OUT pins could fix the problem so it could be a solution. What I want is to understand the problem so I want to know if the 9HT10-32.768KAZY-T values are “border line” for the F103 uC (and a slight variation in the last lot of production of the oscillator raise the LSE startup issue), what really is or how is working the 5M feedback resistor or, in general, what may cause this issue.

Thanks for your time.

Francesco

[AScha.3]

Hi,

>external 10M resistor between LSE OSC_IN and OSC_OUT pins could fix the problem

Did you check on not working LSE ?  + 10M , then good working ? 

[Peter BENSCH]

Welcome ​@FrancescoV, to the community!

a small note: you forgot to also specify the respective value of the shunt capacitance C0 for the data. However, as the datasheets are currently available online, I was able to determine them, and the complete values for recalculation are:

• MC-306 32.768K-E3
  • ESR=50k max
  • CL=6pF
  • C0=0.95pF
• 9HT10-32.768KAZY-T
  • ESR=70k max
  • CL=7pF
  • C0=1pF  

gmargin is therefore 12.387 for the MMC-306, which is more than sufficient, but only 6.582 for the 9HT10, which is only slightly greater than the minimum of 5.

It could now be that e.g. your layout is not quite optimally designed, which was probably compensated for by the significantly larger gain margin, but is now leading to the observed problems.

Unfortunately, unlike the newer STM32 devices, the STM32F103 does not yet have an LSE with adjustable drive strength, so your only options are to check the layout and/or use a crystal with an ESR of less than 60k, ideally less than 50k. However, make sure that C0 does not become significantly greater than 1pF, because that would worsen the gain margin again.

You’re welcome to insert a picture of the layout section around the crystal here, and then we can check it together. Alternatively, take a look at the Knowledge Base article:

Regards
/Peter

[FrancescoV]

Hello ​@Peter BENSCH,

thanks for your reply.

I have done those calculations but I cannot figure out if gmargin=12 was sufficient or not.

I read the paragraph “2.2.6 LSE startup in harsh environments” int he ST errata ES0346 which stands that “It is recommended to mount an additional parallel feedback resistor (from 16 MΩ to 22 MΩ) on board to help the oscillation startup in all cases”: my doubt is if the gmargin consideration is sufficient to guarantee the LSE to function correctly.

I have done some tests to figure out if the greater ESR of the 9HT10-32.768KAZY-T could be the main actor in this issue; I add a resistor between the crystal and the capacitor on the OSC_OUT side to (try to) simulate a grater crystal ESR. The value of the resistance is 56k, so 75% greater than the “true” ESR. The LSE seems to start correctly every time i power up the MCU so, or this is not a (mainly) ESR issue or this is not the right way to simulate a larger crystal’s ESR. Do You have some hint?

Thank You again

Regards

Francesco

[FrancescoV]

The LSE seems to start correctly every time i power up the MCU so, or this is not a (mainly) ESR issue or this is not the right way to simulate a larger crystal’s ESR.

In the paragraph 3.8 of the AN2768 I found that this is definitely not the way to simulate a greater ESR of the crystal but is the way to estimate it’s negative resistance.

[Peter BENSCH]

The ES0336 is more related to start-up problems under the special environmental conditions mentioned. However, it can do no harm to connect such a parallel resistor. I do, however, suspect that this will not make any difference in your case.

A series resistor for the crystal, i.e. the way you have inserted it between crystal and CL, only very roughly imitates a higher ESR, because the resistor not only increases the losses of the crystal, but also changes the start-up behaviour, affects the oscillator amplitude, shifts the load on the inverter/amplifier, and can also alter the frequency. It is always important to bear in mind that ESR appears only as one partial parameter in the equivalent circuit. You should not try to force the current crystal, with its somewhat high ESR (on an STM32F103), to oscillate at all costs, but rather focus on a different crystal with the recommended parameters.

Regards
/Peter

[STOne-32]

Dear ​@FrancescoV , all,

Interesting discussion. My comments are :

 

1. can you explain what means do not start at all ?  I have seen in many designs that software loop of timeout is set for example to 2 or 5 seconds and if removed the LSE will start but with a long start-up  - more than usual.
2. why changing directly the CL1=CL2 from 3.3pF to 10pF … I do not see a rationale in your design . I would expect only 5.3pF or 5.6pF not more to keep same equivalent loop as your working PCB . May I missed something ?  Theory says - your Cs = 12-3.3pF = 8,7pF so 14pF -8,7pF = 5,3pF
3. The errata is only present on our STM32F103 XL density devices and was written by me :-) many years ago . We have  a weakness on that LSE design due to die size creating a leakage in OSC32_IN that is impacting the start-up condition at Cold in particular and or with water droplets or Frost. Adding that parallel high resistance will help to compensate the leakage path and will relax a bit the oscillation margin.

hope it helps and let me know your feedbacks.

Regards,

STOne-32