STM32U3C5: HSP Interrupts

[AQB]

I am trying to generate an interrupt when the HSP finishes a processing list so that I don’t need to poll it. However, I can’t seem to figure out how to do this.

There are some things in the STM32U3 reference manual that make me confused:

In section 19.4.12 HSP interrupt controller (HITC), there are four interrupt lines:
• An interrupt line handling errors (hsp_err_it)

• An interrupt line handling various hardware events (hsp_evt_it)

• An interrupt line handling events generated by the SPE processing (hsp_fwevt_it)

• A global interrupt is asserted when one of the previous interrupts is asserted (hsp_it)

However, in Section 19.3 HSP Implementation, Table 143 shows that neither hsp_err_it, hsp_evt_it, nor hsp_fwevt_it are implemented in the U3 series. If this is the case, does that mean that hsp_it is just never asserted? Is it possible to notify the application when a processing list has finished without polling for a flag?

Section 5.13.5 of UM3360: HSP processing functions says that the SET_FLAG function can generate an interrupt when it sets a bit in HSP_PFCTEVT_ISR, but is this mapped to one of the unimplemented lines?

I am using STM32U3C5

[AQB]

My workaround for now is to use a SetTrgo function at the end of the processing list, and this Trgo triggers a DMA channel to move a single dummy byte. I can then use the DMA’s callback as the HSP complete callback.

[FBL]

Hi ​@AQB 

Only global interrupt is implemented in STM32U3C5/B5. hsp_err_it hsp_fwevt_it hsp_evt_it are not connected. So to notify about a HW event or processing list completion, you need to poll for a flag as implemented in HAL.

It is not possible to use the SET_FLAG command to interrupt the CPU on STM32U3C5/B5, and a polling mechanism is required.

[PVX]

Hi @AQB,

You can indeed use the SET_FLAG command to signal the end of an HSP processing list (or any other relevant user event) by interrupting the CPU on STM32U3C5/B5, as you originally planned to do.

Polling is usually not necessary with the HSP because it is designed for efficient interrupt-driven synchronization with the CPU and other HW elements.

The ‘unconnected’ lines hsp_err_it, hsp_fwevt_it, hsp_evt_it lines are actually wired-or together to create the global interrupt line hsp_it, as shown in diagram 19.4.12 in the reference manual, so any condition that triggers one of the Iines (an error, a hardware event or a FW processing event) will also trigger the HSP global interrupt line.

To achieve the desired effect, you will need to enable the HSP_PFCTEVT_ISR register bit corresponding to the processing event number you are going to trigger in your application, in the range 0-31.

Please note that, since the global interrupt may be triggered by other conditions (e.g. HSP errors), it is advisable to check the HSP_ERR_ISR and HSP_EVT_ISR registers for possible HW events before checking the HSP_PFCTEVT_ISR register for FW processing events inside the CPU-side ISR.

Best regards and good work on your application 🙂