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Could you please provide information on the DMIPS/MHz performance of the A35 core in the STM32MP23? Is this specified in any documentation?

I'm testing the VL53L9CX sensor with the X-NUCLEO-53L9A1 board. I'm conducting my tests with the Nucleo H561ZI board and the X-CUBE-53L9A1.zip software stack.The sensor works correctly indoors. However, outdoors, when moving from shade to full sun, the sensor malfunctions.The software returns the error: VL53L9_ERROR_INVALID_STATE. why?In the datasheet, this isn’t a description of all registers? So I cannot clear this error without resetting the device!Can have a complet datasheet of the product?

I am looking for the STEVAL-VL53L9 evaluation board for vl53l9cx, but it is out of stock at all distributors I checked.could you please let me know the expected availability / ETA, where i can buy it or, if there is any similar alternative board with same specs.

We have been evaluating the pre-trained model yamnet_e1024_64x96_tl_qdq_int8.onnx from the STM32 Model Zoo (ESC-10 variant) and noticed a potential discrepancy between the class label order in the provided YAML configuration and the actual output behaviour observed on target.While the model itself appears to perform well, the mapping between output indices and class names does not seem to match the order documented in the YAML file. Observed behaviour:The YAML file lists the classes as:0: dog1: chainsaw2: crackling_fire3: helicopter4: rain5: crying_baby6: clock_tick7: sneezing8: rooster9: sea_waves However, on our target, the outputs appear to correspond to the following order:0: chainsaw1: clock_tick2: crackling_fire3: crying_baby4: dog5: helicopter6: rain7: rooster8: sea_waves9: sneezing This is consistent across multiple input samples, which makes us suspect a systematic label remapping rather than random misclassification. Preliminary hypothesis:We suspect that this could be caused

Hello, I am using an STM32H750I-DK Discovery board with LAN8742 PHY, MII mode, FreeRTOS and LwIP.Ethernet works initially: the STM32 IP appears in arp -a and I can ping it. After some time, the ARP entry disappears and ping gives Request timed out or Destination host unreachable.I have already checked the IP configuration, MII configuration, PHY link, DMA, MPU/cache, and tried disabling RTP traffic, but the issue still occurs.What could cause the STM32H750 Ethernet connection to stop responding to ARP and ping after working normally for some time? What should I check next?

Hello, I am currently developing a test environment based on the NUCLEO-F411RE evaluation board (MB1136C).As part of this project, I am designing a mechanical enclosure with modular plastic components, which I plan to 3D print. While several enclosure designs are available on Thingiverse, none of them meet the specific requirements of my project. Could you please provide, if available, the official CAD files (STL or STEP format) for the MB1136C?This would allow me to integrate the board's exact dimensions into my assembly and ensure proper tolerances with my existing parts. Thank you for your time and assistance. I look forward to your response. Best regards,Alexandre

Hi all, I’ve seen in other manufacturers MCUs( sometimes) calibration values that may get lost if I wipe out the whole chip. It was long long ago.I’m new to this STM32U5 series. I’m working with the STM32U5G9J-DK2 kit. I’m porting the LCD stuff to my empty program. But I’m debugging and sometimes I need to go back and program the BSP example. Then I go back to my program and the thing is it keeps showing the demo screen (from the BSP example)  even though I don’t have it in my program. It goes away if I unplug the USB cable. I was wondering if instead I can use the STM32cubeprogrammer and use the erase full chip button instead? Am I gonna lose anything important? Thanks

Hello,I am working on a custom application with BLE OTA on the Nucleo WB55RG. The OTA loader is placed at 0x08000000. My main application is linked to start at 0x08007000.In normal mode, the main application runs an ADC test and continuously prints ADC values. I added a hardware OTA trigger on pin PC2. When PC2 is driven high, the application prepares the BLE OTA request and then calls NVIC_SystemReset(). The OTA request is passed to the loader at the start of SRAM.After this, the OTA loader starts correctly. The loader detects the OTA request from SRAM. The loader erases the application flash area starting from sector 7, corresponding to address 0x08007000. The loader then attempts to initialize the BLE stack and start advertising.The issue is that BLE advertising does not start when entering OTA mode after the NVIC_SystemReset(). Pressing the on-board reset button also does not make BLE advertising start. However, if I completely power cycle the board by removing USB power and reconn

I am using STM32CubeIde, No RTOS, USART1, RX DMA (Circular), TX DMA in normal mode with DMA_IT_HT disabled.I’ve got main loop periodically outputting a simple message on the USART. System appears to hang when commanded to change baud. I’ve tried perhaps dozens of variations that have been recommended by “STM32 Sidekick” and Google AI.  Most work with the debugger connected.  None work without the debugger which is making this difficult to troubleshoot.  Sidekick example shown below.  // 1. Wait for any ongoing transmissions to finish safely // This prevents splitting a character mid-air. while (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) == RESET) { // Optional: Implement a timeout mechanism here } // 2. Temporarily de-initialize the UART peripheral // This turns off the UART but keeps your GPIO and DMA settings intact. if (HAL_UART_DeInit(huart) != HAL_OK) { return; //H

Hi everbody,we are using an STM32H573 with ST Secure Manager and would like to perform the final Product State transition from TZ-CLOSED to CLOSED at the end of production.At this point, the device is already assembled and SWD/JTAG is no longer accessible. Therefore, we would like to trigger the transition through an authenticated internal command from the Non-Secure application.From the documentation, we understand that:PRODUCT_STATE is controlled via Flash Option Bytes. The Non-Secure application cannot directly modify the relevant Secure Flash registers. We could not find a documented Secure Manager runtime API for changing the Product State.Could you please clarify:Is there an existing Secure Manager API to perform TZ-CLOSED → CLOSED at runtime without SWD/JTAG? If not, can this be implemented via an OEM Secure Module? Is an OEM Secure Module allowed to modify the PRODUCT_STATE Option Byte?Thanks and best regardsMario

Hi again,Since the new version of ST Community I can't find my previous post, so I'm creating a new topic to follow up on the old one. The replies from @AScha.3 and @Brian TIDAL on that thread helped me a lot before it disappeared.As I mentioned, I'm a beginner in this field. The full context is in my earlier post:I have just one more question. You mentioned that building an external antenna is easy, but is it really doable for a beginner? I'd like to know whether I can realistically do it myself if I buy the right equipment to measure inductance, or whether I need an expert to guide me.Also, in addition to AN6065, I found AN2866, which is more readable in my opinion and provides a step-by-step procedure. I don't understand everything yet, but I'll work through it.Thanks!

Hello Team,We are currently developing a custom board based on the STM32MP255 and have encountered a routing challenge.According to the STM32MP255 DDR routing guidelines, the single-ended trace impedance should be 55 Ω. However, after optimizing the PCB stack-up and routing, the closest value we have been able to achieve using the Saturn PCB Toolkit is 70 Ω.Could you please confirm whether this deviation from the recommended impedance is acceptable? Specifically, we would like to understand:Will this impact DDR functionality, signal integrity, or overall system reliability? Is 70 Ω within an acceptable tolerance for the STM32MP255 DDR interface, or would you recommend modifying the PCB stack-up to achieve the target 55 Ω?Your confirmation and guidance will help us proceed with confidence before finalizing the board design.DDR Routing imageMeasuring toolLayer Stack-up 

Hello,I would like to test the VL53L9CX using the GUI interface compatible with the X-NUCLEO-53L9A1 board. This software appears to be the STSW-IMG052. The ST webpage for this software returns a 404 error. Were there issues with using this software that led to the download being suspended, or is it simply a broken link on ST's servers?Thanks for your answers,Christophe

I'm working on an STM32G0B1RE and have a question regarding PWM generation and timer limitations. Current Hardware ConfigurationThe hardware design is already fixed, so changing pins is difficult. Current PWM signals are routed as follows:    PA8 -> TIM1_CH1    PA9 -> TIM1_CH2    PC11 -> TIM1_CH4    PC9 -> TIM3_CH4From CubeMX I confirmed that:    PA8 -> TIM1_CH1 only    PA9 -> TIM1_CH2, TIM15_BKIN    PC11 -> TIM1_CH4 only    PC9 -> TIM3_CH4, TIM1_CH2My software currently uses TIM1_CH1, TIM1_CH2, and TIM1_CH4 simultaneously. What I ObservedI have a PWM abstraction layer that allows setting frequency per logical PWM device. However, after reviewing the implementation and STM32 timer architecture, I realized that changing the frequency of one TIM1 channel modifies the timer ARR value, which affects all channels on TIM1.     DeviceA -> TIM1_CH1    DeviceB -> TIM1_CH2    DeviceC -> TIM1_CH4If I execute:    setFrequency(DeviceA, 1000);and later:    setFrequen

Wondering if VL53L9CX generates per-pixel histograms?It looks like there is no relevant information either in the datasheets or the released firmware. Many thanks,Z

I can't decipher the silkscreen markings on this chip. Could you please help me confirm?This chip looks like it's from ST, but I didn't see the ST logo. I suspect it's an abbreviation for STM32G473ME, but I can't confirm it, and the chip's datasheet doesn't provide detailed information on device markings.

I would like to ask if there’s any major differences when making the chips in STM32G4 series, like the STM32G441 to STM32G473 for example

I try to do power wirign for the STM32N645 but unfortunately the AN and the User Guide are not perfectly clear and somewhat incomplete.When I understand it correct, the STM32N6 generates the VDDCORE voltage of 0,89V internally, so all I have to do with the VDDCORE-pins is to connect them with each other and to couple each of them with 100 nF to ground, right? For this I need a specific SMPS configuration which lets the MCU generate this voltage. Here I have a description in the AN and the User Guide which shows some wiring scheme named “Configuration when using SMPS (option 1)” that consists of two inductances and a capacitor and external 1.8V feed into VDDSMPS input.My problem here: the wiring scheme of the development board of that MCU is completely different to what the documentations say. And: neither in the AN nor in the User Guide there are any values for these components. So the question is: what wiring should i use with which component values to let the MCU generate the VDDCORE

We have been trying to access DBGMCU on an STM32H7A3 via software. The background is that the project shares code that in an other project runs on an H743 and for example needs to adjust how it interacts with the flash.We’re now experiencing the strange behaviour that when a debugger is connected the DBGMCU ID code reads correctly as 0x10076480. When no debugger is connected it reads as zero (0x00000000). This is the case when debugging using GBD or when connecting via STM32CubeProgrammer. Connecting via STM32CubeProgrammer to an already running processor makes it readable. After disconnecting it reads zero again.We’ve tried accessing the ID both viaAL_GetDEVID()HAL_GetREVID()as well as directly viaDBGMCU->IDCODEwith the same results.Testing access to the writable parts of DBGMCU show a similar behavior where it works when connected to the debugger but not otherwise.Now we are wondering if there are any clock or power configurations that could lead to such a behavior. We’ve seen sim

All the microcontrollers in this comparison test are STM32L072CZT6, and they used the same firmware, PCB, and testing procedures. The test results are as follows:PCB new batch MCU – UID: 16473531-32333338-003C0041This is the STM32L072CZT6 from the new batch we received. Without making any changes to the firmware, the LED indicator flashes blue (instead of green), and the current consumption in sleep mode is about 6.44 mA.Previously manufactured batch MCU – UID: 19513931-30383135-0017004EThe LED flashes green, and the current consumption in sleep mode is about 117.97 µA.DigiKey STM32L072CZT6 – UID: 04473234-34313430-00160034This component was purchased directly from DigiKey. The LED flashes green as expected, and the current consumption in sleep mode is about 43.07 µA. The newly supplied components show significant performance differences compared to the reference components obtained from DigiKey.The difference in sleep current is extremely noticeable: the former is around 6.44 mA, whil

Hello STM32N6 Tech support I am writing with reference to power on sequence. My power sequence is as follow1. First VDDA1V8_AON, VBAT and VDD is applied. My VDDIO4 & VDDIO5 is also connected with VDD.2. VDDCORE is supplied from an external SMPS step-down converter. We applied VDDCORE when the PWR_ON signal is high. VDDCORE is also connected with VDDCSI3. On the same PWR_ON my VDD3V3 is switched on. It is connected with VDD33USB.4. On the same PWR_ON my VDDA1V8 is connected. However, the input voltage of VDDA1V8 (linear regulator) is connected with VDD3V3. VDDA1V8 is connected with VDDA18CSI, VDDA18USB, VDDA18ADC.Can you please explain the above mentioned sequence will work for powering on STM32N6. I need comments on the following.1. Step 3 & Step 4 is not strictly defined in Getting started with hardware development for STM32N6 MCUs - Application note.pdf and an6000-how-to-build-the-discrete-power-supply-for-stm32n6-mcus-stmicroelectronics.pdf.2. I am not following any power do

When testing the gyroscope of this product (LSM6DSV80X) we noticed that the noise density on each gyro axis is different with z being the lowest. This was observed on the dev-board (STEVALSMKI109DA) both in high performance and HAODR modes. The ratio between x and z is particularly noteworthy. Is there an explanation for this? The datasheet only reports one noise density so I am assuming that all axis should be the same. The same characteristics has been found on two different units. N.B.: Plain implies high performance. Rn is the noise density 

Hi,I have a SoM based on STM32MP135c (QSMP-1351) and I try to enable the secure boot using STM32_Programmer_CLI (STM32CubeProgrammer v2.22.0)Here is the flash layout file used before updating OTP:#opt  Id   Name  Type  Device Offset Binary-    0x01  fsbl-boot    Binary none  0x0   tf-a-loader.stm32-    0x03  fip-boot    FIP   none  0x0   fip-loader.binI can write PKHTH without any issue:STM32_Programmer_CLI -c port=usb1 -otp write word=0x18 value=0x????????STM32_Programmer_CLI -c port=usb1 -otp write word=0x19 value=0x????????STM32_Programmer_CLI -c port=usb1 -otp write word=0x1a value=0x????????STM32_Programmer_CLI -c port=usb1 -otp write word=0x1b value=0x????????STM32_Programmer_CLI -c port=usb1 -otp write word=0x1c value=0x????????STM32_Programmer_CLI -c port=usb1 -otp write word=0x1d value=0x????????STM32_Programmer_CLI -c port=usb1 -otp write word=0x1e value=0x????????STM32_Programmer_CLI -c port=usb1 -otp write word=0x1f value=0x????????When I want to lock device, I use the comm

We are currently evaluating a board design based on the STM32MP253FAK3, and would like to confirm the following regarding the DDR4 memory configuration.[Configuration under consideration]MPU：    STM32MP253FAK3Memory devices：    Two DDR4 8 Gbit x8 devices (1 GByte each), mounted as two separate packagesBus width：    16-bit (Byte0 = device #1, Byte1 = device #2)Rank configuration：    Single rank (CS0 / CKE0 / ODT0 shared by the two devices)Total density：    2 GByte[Questions]1. Support for this topologyIs the "two x8 devices / 16-bit" configuration — that is, forming a 16-bit bus using two x8 devices in separate packages — supported on the STM32MP253FAK3?In AN5724 (Guidelines for DDR memory routing on STM32MP2 MPUs), only the following two configurations are described for DDR4:16-bit interface: one x16 device connected point-to-point (Section 3.4)32-bit interface: two x16 devices connected in a fly-by topology (Section 3.2)We could not find any description of a configuration using x8 dev

HelloI’m using TouchGFX 4.26.0 on a STM32H747 and want to use RGB compression of the bitmaps to get the size of the firmware image smaller. To prevent performance loss, all bitmaps are loaded into the cache at startup. I have enough free SDRAM for the cache, so this is the easiest method and doesn’t require manual maintenance when adding / removing bitmaps to the project.Because the displays native orientation differs from the application orientation, image rotation is set to 90° by default.The code to load the bitmaps is shown below. This function is called at the end of TouchGFXHAL::initialize()​void loadAllBitmapsIntoCache(){ const uint16_t totalBitmaps = BitmapDatabase::getInstanceSize(); for (uint16_t id = 0; id < totalBitmaps; ++id) { touchgfx::Bitmap bmp { id }; auto format = bmp.getFormat(); bool ok; if (format == touchgfx::Bitmap::BitmapFormat::COMPRESSED_RGB565 || format == touchgfx::Bitmap::BitmapFormat::COMPRESSED_ARGB8888 ) { ok = touchgfx::Bitmap::decompressR