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September 4, 2026
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DMIPS/MHz of the A35 core in the STM32MP23

  • September 4, 2026
  • 2 replies
  • 86 views
  • Could you please provide information on the DMIPS/MHz performance of the A35 core in the STM32MP23?
    Is this specified in any documentation?
Best answer by PatrickF

Hi,

Core performances values are not in documentation as because usually those simple benchmark run full from cache, so every MPUs with Cortex-A35 will have same figures.

ARM state about 1.7-1.78 DMIPS/MHz/core (but some sources mention up to 2.5).

FYI, we measure Coremark of Cortex-A35 with GCC compiler at s about 3.0 Coremark/MHz/core.

Remind that Cortex-A35 is a low power core, so performance is lower than some other Cortex-A cores.

 

Could you share the rationale to ask for DMIPS/MHz ?

Note that overall Linux performance is not pure processor performance, it is also linked to external memories interfaces choices (Flash, DDR), internal HW accelerators, internal bus architecture, SW optimization, etc.. 

 

Regards
 

2 replies

mƎALLEm
ST Technical Moderator
September 4, 2026

Hello,

That question needs to be asked in STM32 MPU Products forum. There is a big difference between MCU and MPU.

I’ve already moved your question to it.

To give better visibility on the answered topics, please click "Best answer" on the reply which solved your issue or answered your question.
PatrickF
PatrickFBest answer
ST Employee
September 7, 2026

Hi,

Core performances values are not in documentation as because usually those simple benchmark run full from cache, so every MPUs with Cortex-A35 will have same figures.

ARM state about 1.7-1.78 DMIPS/MHz/core (but some sources mention up to 2.5).

FYI, we measure Coremark of Cortex-A35 with GCC compiler at s about 3.0 Coremark/MHz/core.

Remind that Cortex-A35 is a low power core, so performance is lower than some other Cortex-A cores.

 

Could you share the rationale to ask for DMIPS/MHz ?

Note that overall Linux performance is not pure processor performance, it is also linked to external memories interfaces choices (Flash, DDR), internal HW accelerators, internal bus architecture, SW optimization, etc.. 

 

Regards
 

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