STM32G0B1RE - Need Independent PWM Frequencies on TIM1 Channels (PA8, PA9, PC11)
I'm working on an STM32G0B1RE and have a question regarding PWM generation and timer limitations.
Current Hardware Configuration
The hardware design is already fixed, so changing pins is difficult. Current PWM signals are routed as follows:
PA8 -> TIM1_CH1
PA9 -> TIM1_CH2
PC11 -> TIM1_CH4
PC9 -> TIM3_CH4
From CubeMX I confirmed that:
PA8 -> TIM1_CH1 only
PA9 -> TIM1_CH2, TIM15_BKIN
PC11 -> TIM1_CH4 only
PC9 -> TIM3_CH4, TIM1_CH2
My software currently uses TIM1_CH1, TIM1_CH2, and TIM1_CH4 simultaneously.
What I Observed
I have a PWM abstraction layer that allows setting frequency per logical PWM device. However, after reviewing the implementation and STM32 timer architecture, I realized that changing the frequency of one TIM1 channel modifies the timer ARR value, which affects all channels on TIM1.
DeviceA -> TIM1_CH1
DeviceB -> TIM1_CH2
DeviceC -> TIM1_CH4
If I execute:
setFrequency(DeviceA, 1000);
and later:
setFrequency(DeviceB, 5000);
the second call changes the TIM1 ARR register, causing all TIM1 channels to run at 5 kHz. This seems expected since TIM1 channels share:
PSC
ARR
Counter
and only have independent CCR registers.
Requirement
Ideally I would like something like:
PA8 (TIM1_CH1) -> 1 kHz
PA9 (TIM1_CH2) -> 2 kHz
PC11 (TIM1_CH4) -> 5 kHz
running simultaneously.
My Questions
1. Is there any STM32 timer configuration or mode that allows different PWM frequencies on TIM1_CH1, TIM1_CH2, and TIM1_CH4 simultaneously while using the same TIM1 peripheral?
2. My understanding is that with the current routing I effectively have only:
TIM1 -> PA8, PA9, PC11
TIM3 -> PC9
which means only two independent hardware PWM frequency domains are available?
Can someone confirm whether this understanding is correct and suggest the best approach?
Thanks in advance.
