STM32MP255 DDR4 Routing

[TejasN]

Hello Team,

We are currently developing a custom board based on the STM32MP255 and have encountered a routing challenge.

According to the STM32MP255 DDR routing guidelines, the single-ended trace impedance should be 55 Ω. However, after optimizing the PCB stack-up and routing, the closest value we have been able to achieve using the Saturn PCB Toolkit is 70 Ω.

Could you please confirm whether this deviation from the recommended impedance is acceptable? Specifically, we would like to understand:

• Will this impact DDR functionality, signal integrity, or overall system reliability?
• Is 70 Ω within an acceptable tolerance for the STM32MP255 DDR interface, or would you recommend modifying the PCB stack-up to achieve the target 55 Ω?

Your confirmation and guidance will help us proceed with confidence before finalizing the board design.

DDR Routing image

Measuring tool

Layer Stack-up

 

[PatrickF]

Hi ​@TejasN 

I fear 70 ohms is too high.
If you fill comfortable with 70 ohms and your simulations shows signal integrity is acceptable, you could keep like this, but we have no experienced/tested a 70 ohms PCB.

From ST side, we recommend that stack-up or track width to be changed to approach the recommended 55 ohms.

Please refer to  AN5724 Guidelines for DDR memory routing on STM32MP2 MPUs
High-speed SI simulations using IBIS and board-level simulations using HyperLynx® SI on STM32 MCUs and MPUs
and examples provided inside STM32MP2 Series DDR memory routing guidelines examples

 

Regards.