STM32N6 Power On sequence

[Zaeem-Ahmed]

Hello STM32N6 Tech support

I am writing with reference to power on sequence. My power sequence is as follow
1. First VDDA1V8_AON, VBAT and VDD is applied. My VDDIO4 & VDDIO5 is also connected with VDD.
2. VDDCORE is supplied from an external SMPS step-down converter. We applied VDDCORE when the PWR_ON signal is high. VDDCORE is also connected with VDDCSI
3. On the same PWR_ON my VDD3V3 is switched on. It is connected with VDD33USB.
4. On the same PWR_ON my VDDA1V8 is connected. However, the input voltage of VDDA1V8 (linear regulator) is connected with VDD3V3.

VDDA1V8 is connected with VDDA18CSI, VDDA18USB, VDDA18ADC.
Can you please explain the above mentioned sequence will work for powering on STM32N6. I need comments on the following.
1. Step 3 & Step 4 is not strictly defined in Getting started with hardware development for STM32N6 MCUs - Application note.pdf and an6000-how-to-build-the-discrete-power-supply-for-stm32n6-mcus-stmicroelectronics.pdf.
2. I am not following any power down sequence. Is it very necessary to follow. Please suggest.

[mƎALLEm]

Hello ​@Zaeem-Ahmed and sorry for the late reaction,

I’m escalating your question internally for review over this internal ticket CDM0065534 (not accessible by community users).

I’ll share the answer as soon as I have a feedback from the team.

[mƎALLEm]

This is the reply from the team:

1. Regarding the power-up sequence, you should refer to the latest revision of AN5967 “Getting started with hardware development for STM32N6 MCUs”, specifically the chapter "Main and Auxiliary Supplies Sequencing".

2. Regarding the power-down sequence, the recommended sequence must be followed. Otherwise, it may generate inrush currents between the supplies due to the power isolation requirements implemented by this sequencing. This could create current spikes and lead to an incorrect or unstable power-down state.

Hope that answers your questions.