DDR4 Memory Configuration Using STM32MP253FAK3
We are currently evaluating a board design based on the STM32MP253FAK3, and would like to confirm the following regarding the DDR4 memory configuration.
[Configuration under consideration]
MPU： STM32MP253FAK3
Memory devices： Two DDR4 8 Gbit x8 devices (1 GByte each), mounted as two separate packages
Bus width： 16-bit (Byte0 = device #1, Byte1 = device #2)
Rank configuration： Single rank (CS0 / CKE0 / ODT0 shared by the two devices)
Total density： 2 GByte
[Questions]
1. Support for this topology
Is the "two x8 devices / 16-bit" configuration — that is, forming a 16-bit bus using two x8 devices in separate packages — supported on the STM32MP253FAK3?
In AN5724 (Guidelines for DDR memory routing on STM32MP2 MPUs), only the following two configurations are described for DDR4:
16-bit interface: one x16 device connected point-to-point (Section 3.4)
32-bit interface: two x16 devices connected in a fly-by topology (Section 3.2)
We could not find any description of a configuration using x8 devices.
2. DDR initialization and training software flow
Does the DDR initialization and training software flow (DDRCTRL configuration → DDRPHYC configuration → PHY training firmware load → 1D/2D training → transition to mission mode) work correctly with the "two x8 devices / 16-bit" configuration (a 16-bit bus formed by two x8 devices, single rank, 2 GByte total)?
We would appreciate your confirmation on the above.
