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###### · 2024-07-15

Hello,Are there any resources similar to AN3364, that describe the migration directly from F4 to F0?Thanks.

###### · 2024-07-02

Hello,Has anyone seen ADC noise generated by the 50 MHz RMII clock (PA1) affecting the measurement on ADC1_IN0 (PA0)? (approximately 100 codes in 4096).If so does anyone had a fix to suppress it?All other ADC channels used do not have the same level ...

###### · 2024-05-23

Hello,I've been trying to write my own HAL to replace the STM32 HAL and recently I have been trying to write an LwIP interface, with guidance from this forum and the examples provided by ST and other users.My Individual files compile fine, including ...

###### · 2024-04-19

Hello,Just wondering if anyone knows the reason for the duplicate writes to the following registers in the HAL Ethernet code please?ETH->MACCRETH->MACFCRETH->DMAOMRETH->DMABMRIn the example shown below (from HAL code) the DMA0MR register is written t...

###### · 2024-02-29

Hello,I've read several forum posts commenting on the STM32 HAL management of LWIP, particularly ethernetif.c and trying to understand the interrupt driven zero copy examples. For reference in my application I do not use RTOS.After updating cube, and...

###### · 2024-07-16

@waclawek.jan Thanks for your helpful answer.I would only disagree with the following statement (if it was in regards to my question, that is)"F0 and 'F4 are at the very opposite ends of the spectrum, it does not make sense to migrate an application ...

###### · 2024-07-16

"Doesn't combining Tables 2 & 4 give you F4 vs F0:"Sort of... Taking the ADCs as an example:F1 vs F0F1 vs F4This tells me that the ADC is different to the F1 on both the F0 and F4. But it doesn't tell me if the F0 and F4 are the same (I suspect not)...

###### · 2024-07-05

Might not be relevant, but what is the state of your ethernet NRST pin?This could either be its own GPIO output, or you may have linked it to a push button? NRST should be controlled in user code to enable the PHY.It might be that your board has an i...

###### · 2024-07-03

Thanks.We've perhaps been a bit remiss in our prototyping, and should have checked this earlier...We require 10 ADC channels, basically we did a lot of initial work testing to get the ADC channels working within desired spec through the PCB design lo...

###### · 2024-07-02

Thanks, the risk of crosstalk is what we have suspected.The source impedance of PA0 is directly from a signal conditioning OpAmp output.VDDA and VSS are in close proximity due to the layout of the package, so the RefClk trace has tried to be routed a...

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Migration from F4 to F0 - Resource Request?

ETH_REF_CLK (PA1) noise / crosstalk on ADC1_IN0 (PA0)?

LWIP Project Settings Compilation Error No HAL No SYS

ETH_SetMACConfig and ETH_SetDMAConfig function query

Ethernetif.c in STM32f4 cube FW_F4 V1.28

Re: Migration from F4 to F0 - Resource Request?

Re: Migration from F4 to F0 - Resource Request?

Re: STM32F407 with LAN8742A custom board init issue

Re: ETH_REF_CLK (PA1) noise / crosstalk on ADC1_IN0 (PA0)?

Re: ETH_REF_CLK (PA1) noise / crosstalk on ADC1_IN0 (PA0)?