STM32H747 freezes waiting for VOSRDY

[TDK]

I'm trying to boot the M7 core on a STM32H747 with a 480MHz clock rate. I have the project and clock settings configured in STM32CubeMX.  When ran, the program freezes while waiting for the VOSRDY flag to be set, which never happens.

The code appears to be doing everything it should per the reference manual:

The sequence to activate the VOS0 is the following:

1. Ensure that the system voltage scaling is set to VOS1 by checking the VOS bits in PWR D3 domain control register (PWR D3 domain control register (PWR_D3CR))
2. Enable the SYSCFG clock in the RCC by setting the SYSCFGEN bit in the RCC_APB4ENR register.
3. Enable the ODEN bit in the SYSCFG_PWRCR register.
4. Wait for VOSRDY to be set.

Once the VCORE supply has reached the required level, the system frequency can be increased.

The code is as follows:

 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
 while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} // <--- FREEZES HERE

 which runs this:

  if((__REGULATOR__) == PWR_REGULATOR_VOLTAGE_SCALE0) \
  { \
   MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); \
   /* Delay after setting the voltage scaling */ \
   tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \
   MODIFY_REG(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN, SYSCFG_PWRCR_ODEN); \
   /* Delay after setting the syscfg boost setting */ \
   tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \
  } \
 

I've verified the SYSCFGEN bit in RCC_APB4ENR is set. However, VOSRDY never gets set.

I've also verified the __HAL_PWR_GET_FLAG macro is checking the right thing.

I get the same behavior if I try to change the clock to 400MHz (VOS1), so I don't think the issue is specific to VOS0.

This is on a STM32H747I-DISCO board.

What could be wrong?

[Neuromod]

Same problem here with a STM32H743. I'm trying this:

void power_init()

{

    // Enable SYSCFG peripheral clock

    uint32_t apb4enr = RCC->APB4ENR;

    RCC->APB4ENR |= RCC_APB4ENR_SYSCFGEN;

    // Enter VOS1 mode (required before entering VOS0 mode)

    PWR->D3CR |= PWR_D3CR_VOS_Msk;

    while (!(PWR->D3CR & PWR_D3CR_VOSRDY));

    // Enter VOS0 mode;

    SYSCFG->PWRCR |= SYSCFG_PWRCR_ODEN;

    while (!(PWR->D3CR & PWR_D3CR_VOSRDY));

    // Restore previous RCC APB4 clock register state

    RCC->APB4ENR = apb4enr;

}

and it gets stuck on the first VOSRDY loop