STM32F769I-DISC1 only 64Mb accessible?

[FGeig.1]

Hi everyone!

I'm new to the forum so please let me know if I should add more information, etc..

I am using the external SDRAM (MT48LC4M32B2B5-6A, 128Mb) on the STM32F769I-DISC1 board. The SDRAM was configured with CubeMX to use all four memory banks. Everything works fine if I access memory regions from 0xC0000000 to 0xC0800000 (corresponding to 64Mb). If I try to access memory locations beyond 0xC0800000 the MCU ends up in the Hardfault handler.

Has someone else experienced this issue?

What is the easiest way to check if the SDRAM was correctly set up to use 4 memory banks?

Thanks for your help!

[FGeig.1]

I think this is fine, all the memory allocation is taken care of by the FMC and it clearly works for 2 out of 4 memory banks.

Do you happen to have a second board you can use for testing?

Is there a way to check the connection between SDRAM and MCU on the physical board?

I'm sorry I can't give you any better hints...

[Gregory3]

So I did some tests with the PG5 pin (BA1).

If I declare it as a GPIO and set to High/Low, then it responds correctly, i.e. will set to 3.3V or 0V. this means that there is no short circuit on the board.

If the connection between the CPU and SDRAM on that line is ok, I can't tell, because both of the devices are in BGA package and I don't have and access to the pins/vias on the board (buried vias).

I will ask for another HW to try this out (to exclude a PCB issue), but I still think that this has something to do with a wrong initialization...

"I'm sorry I can't give you any better hints..."

Thank you anyway for your help. I really appreciate it =)

Regards,

Gregor

[Gregory3]

I was trying these methods to fix it:

https://www.keil.com/support/docs/3777.htm

Methods 1 and 2 are not working.

Do you know how to enable this option from the 3. method?

[FGeig.1]

Yeah, wrong initialization seems more probable than the specific trace for enabling 4 memory banks being bad...

Maybe you can compare your code to the STM32 example code for an external SDRAM and see if you find any differences.

[FGeig.1]

There should be a field to set compiler options when you are using an IDE but I have mostly used Makefiles to build stuff.

[Gregory3]

Ok, so I was able to add thie option to the compiler in the STM32 IDE.

It's described in here:

https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=&cad=rja&uact=8&ved=2ahUKEwjKsYzfxPbsAhXJAGMBHb7pAokQFjAAegQIARAC&url=https%3A%2F%2Fwww.st.com%2Fen%2Fdevelopment-tools%2Fstm32cubeide.html&usg=AOvVaw17XOKEGK4FjDzWT8PhSQf4

The actual command is the: " -mno-unaligned-access"

But, this also didn't worked...

Now I will dig deeper into the example codes for some clues while in the mean time the second HW is on the way to me (just to make sure, that this is not a pure accident and the BA1 line is not correctly soldered).

Regards,

Gregor

[Gregory3]

So I received another HW to check it and the issue remains the same...

My last chance is to seek for the initialization issue and compare it to the example codes.

Regards,

Gregor

[Gregory3]

Problem solved!

Like always it was a stupid error. In the BSP library I have used (modified BSP "stm32746g_discovery_sdram.h") is a definition of the memory size and bus width.

This needs to be adapted to the right size (0xC100 0000) and to the right bus width I'm using (32 Bit):

/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
 
/**
  * @brief  SDRAM status structure definition
  */
#define   SDRAM_OK         ((uint8_t)0x00)
#define   SDRAM_ERROR      ((uint8_t)0x01)
 
 
#define SDRAM_DEVICE_ADDR  ((uint32_t)0xC0000000)
#define SDRAM_DEVICE_SIZE  ((uint32_t)0x1000000)  /* SDRAM device size in MBytes */
 
/* #define SDRAM_MEMORY_WIDTH            FMC_SDRAM_MEM_BUS_WIDTH_8  */
//#define SDRAM_MEMORY_WIDTH               FMC_SDRAM_MEM_BUS_WIDTH_16
#define SDRAM_MEMORY_WIDTH               FMC_SDRAM_MEM_BUS_WIDTH_32
 
#define SDCLOCK_PERIOD                   FMC_SDRAM_CLOCK_PERIOD_2
/* #define SDCLOCK_PERIOD                FMC_SDRAM_CLOCK_PERIOD_3 */
 
#define REFRESH_COUNT                    ((uint32_t)0x0603)   /* SDRAM refresh counter (100Mhz SD clock) */
 
#define SDRAM_TIMEOUT                    ((uint32_t)0xFFFF)

After that all works like it supose to do :)

Thank you anyway for all the help!

Regards,

Gregor

[FGeig.1]

Nicely done!

Mistakes are never stupid if you learn from them :D

Good luck with your other projects!

Regards