SMT32F7 or STM32H7 FMC SDRAM controller config documentation.

[MEdgerton]

I am using STM32F7 or STM32H7 to test SDRAM using FMC controller. Initially I could ot se a clock output. Seaching here has got that going.

I have tried theSTM32CubeIDE and even set SDRAM bank 2 the same as Bank1 after reading there may be an issue.

So far nothing. I stepped through and see a clock being anabled. It is mapped to PG8 on both H7 and F7 but I see not output there. I have tried various HCLK speeds with no joy.

I saw a message about needing static void BSP_SDRAM_Initialization_Sequence(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command)

but I cannot find a reference to original documentaton so am using it from the github repository.

Also what is the 16-bit byte enable, I already have 16bit wide bus enabled. Thanks for help with this... I see it enles extra lines for how it writes but agin I cannot fd documentation about it. just a presentaion saying everything it can do, but not how to do it!

What simple thing am I missing? Most other things work through STM32CubeIDE.

Thanks,

Mark

[MEdgerton]

Hi Dave, Just back in the lab so thought I'd send the scope plot. This was just a simple toggle pin on the pins detailed. PC2 and PC3 should behave the same. As you can see they clearly do not!

I also noticed that most of ST's examples use Bank2 for SDRAM. Whether this is because of this issue or because they also demo other memory types who knows. Maybe both?

The register is SYSCFG->PMCR that cross links PC2 to PC2_C and PC3 to PC3_C (on H743zi at least.

This is what you are looking for.

Let me know what you find!

Mark

[David Littell]

Sorry for the slow reply. My hardware guys still need to scope the signals but a closer look at the data's behavior in SDRAM points to a stuck address line. Thanks very much for your help.

[David Littell]

...quite the mystery at this point, SDRAM appears reflected every 0x200 bytes. One would think "stuck address line" but the row/column signals are all active. Good times.