SMT32F7 or STM32H7 FMC SDRAM controller config documentation.

[MEdgerton]

I am using STM32F7 or STM32H7 to test SDRAM using FMC controller. Initially I could ot se a clock output. Seaching here has got that going.

I have tried theSTM32CubeIDE and even set SDRAM bank 2 the same as Bank1 after reading there may be an issue.

So far nothing. I stepped through and see a clock being anabled. It is mapped to PG8 on both H7 and F7 but I see not output there. I have tried various HCLK speeds with no joy.

I saw a message about needing static void BSP_SDRAM_Initialization_Sequence(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command)

but I cannot find a reference to original documentaton so am using it from the github repository.

Also what is the 16-bit byte enable, I already have 16bit wide bus enabled. Thanks for help with this... I see it enles extra lines for how it writes but agin I cannot fd documentation about it. just a presentaion saying everything it can do, but not how to do it!

What simple thing am I missing? Most other things work through STM32CubeIDE.

Thanks,

Mark

[MEdgerton]

OK, So I got the clock going by tinkering with the call as it wasn't referencing the hsdram properly. I still need to know how to configure the setting and how this function should be written as it appears it should be generated automatically but isn't.

Side Note: what other devices are like this in cubeIDE or is it find out as you go?

Main think is to find out how this should be written and configured to a particular device as it appears to configure settings already setup and initialised but the CubeIDE code generator.

Many thanks,

Mark

[berendi]

Yes. CubeMX is a black box, you click some settings and it either works as you think it should work, or it does something else.

For more predictable results stick to the reference manual, there are step by step instructions for configuring each peripheral.

[MEdgerton]

Thank you. As elsewhere I have found it looks like PC2 (PC2_C) not switching fast enough. I hav manually set it to connect to PC2 but it doesnt work. PC3_C does switch fast though..... firmware issue with ST?

[MEdgerton]

I fund the reference and checked SYSCFG->PMCR to check that the bits were correctly set (low to enable interconnect between Pxy_C and Pxy. This is correct for PC3_C and PC2_C.

I can while dubggig toggle them. Both become disabled, as epected on the output, showing the interconnect works.

But PC2_C (PC2) remains too slow.

I have checked I am setting it to high speed and this appears to be the case.

Someone else must have experienced this when rigging up SDRAM or similar to a H743 especially on a Nucleo board?

[Tesla DeLorean]

Most people aren't wiring up SDRAM to NUCLEO boards, lot of pins involved, fussy about stubs, timing and pin skew, etc.

Likely to find more people have wired up SDIO/eMMC or QSPI devices.

The people I encounter tend to make a proto-board, or find a close proxy from WaveShare or the assorted vendors at AliExpress or Taobao, etc.

[MEdgerton]

Thanks for the answer. I actually have a nest of wires for SDRAM on a Nucleo-767. It works just fine. Memory tests all ok, removing a pin etc shows a fail as do other tests.

I then made a PCB board up for the Nucleo-H743.

So far I have uncovered that PC2_C on the 144 pin device actually doesn't work at full speed as per datasheet. PC3_C which is meant to be identical does work. So doing this is uncovering a few things.

I have therefor mapped it to another pin but its still not working......

The Waveshare etc is great for a quick prototype. Its still modular through 0.1" pins. Very similar to what I have made,

My memory board is similar but for a Nucleo board, Given the nest of wires works on the Nucelo-767 a PCB on the the H743 should be better.

I'm just looking for any gotchas (like the PC2_C issue above - now raised with ST as a case) with SDRAM on the H743. I have a genuine need for it, and other have done it like me on slower boards. I have backed the speed and settings to be identical but still nothing.

Does the waveshare have demo code as I think it uses a similar SDRAM?

I found this using very similar SDRAM to what I am using.....

Is there any test code for it anyone knows?

Thanks,

Mark

https://www.aliexpress.com/item/1005001608019961.html?aff_fcid=e994db69c06348adb8c33d74cc3aa548-1620658968272-03073-UneMJZVf&aff_fsk=UneMJZVf&pvid=190eb4f1-1768-4a68-8eac-9ce761bb589c&aff_platform=aaf&sk=UneMJZVf&aff_trace_key=e994db69c06348adb8c33d74cc3aa548-1620658968272-03073-UneMJZVf&rmsg=do_not...

[David Littell]

Hi Mark,

Any progress on this? I'm having problems with SDRAM on an H7B3 but the same SDRAM works with an F765 and F777. The H7 FMC clocking is (supposedly) set to run the SDRAM interface at the same rate as with the F7's and the FMC init and SDRAM wakeup steps are identical.

Thanks,

Dave

[MEdgerton]

Hi Dave,

Yes I found the bug and reported it to ST. They acknowledged it but I haven't heard anything since, i.e. fixes etc.

On the H743 144 pin device PC2 actually comes out on PC2_C (the same with PC3 to PC3_C).

This is because it is a multiplexed analogue pin.

I made sure the mux was set correctly. But I found that PC2 that is used for the enable pins when set to SDRAM Bank1 was on a very slow slew rate. Simple code to toggle PC2 and PC3 showed PC2 (output on PC2_C was too slow (PC3_C worked fine)

So I moved to Bank2, which uses different pins (I could have used bank1 and reassigned the pin but am using a Nucleo board for which I'd have had to break the ethernet connection which I need.

Anyway moving to Bank2 (and then setting the addresses accordingly) meant I could avoid pin PC2 (PC2_C) and it all started working.

Its either a low level setting (I delved into the registers for the mux and manually checked/changed them which showed I was changing but not fixing the issue.

I believe on the muxed pins at leats the 144 ping H743zi2 there is a slew rate issue on the pin itself.

Moving away from that pin and it all works and tests out fine to 120MHz in all the tests I've thrown at it.

Hope that helps?

If not let me know how far you have got as I have learnt a lot delving into the registers and settings for the SDRAM etc.

Which SDRAM and exact device are you using?

Mark

[David Littell]

Hi Mark,

Thanks very much for the update. I'm running an STM32H7B3LIHxQ with a single AS4C4M16SA SDRAM on bank 1 at 100 MHz. I've checked the FMC registers against the Reference Manual and they match the working F7 settings.

Our FMC_SDNE0 signal is indeed on PC2 so I guess I should get a scope on it.

Thanks again,

Dave