I2C speed problems

[JonConesa]

Hi everyone,

I’m currently working on an I2C communication setup using the Nucleo-H753ZI DK but the cubeMx document is for the STM32H743BIT (the MCU for my custom board) and aiming to run it in Fast Mode (400 kHz). However, when configuring the I2C clock speed to 400 kHz, the CLK signal becomes unstable, as shown in the attached image.

To ensure the setup is functioning correctly, I ran tests with I2C configured at 100 kHz, and the communication works perfectly in that case.

I’ve also included an image of the system clock configuration in case there’s something that could be optimized.

Does anyone know what might be causing the instability in the CLK signal, preventing proper communication at 400 kHz?

Thanks in advance for your help!

[padawan]

No the SDA and SCL lines at the PCA are 3mA

With 5V on pullup you will burn your cpu.

And 

cause your 5V will go over the pullup to the internal pullup to the vcc of
the CPU. -> burn

padawan

[Andrew Neil]

---

@Ozone wrote:

> For the pull-up, I am using 5V.

A very bad idea.
You must use 3.3V. If the I2c slave(s) are 5V, use level shifters.

---

Pulling-up to 5V for I2C is OK:

https://community.st.com/t5/stm32-mcus-products/stm32-maximium-pin-voltage-in-output-mode/m-p/764074/highlight/true#M271241

[Ozone]

While you are probably correct, the app note in the linked thread recommends a Zener diode between the ext. 5V and VDD.
I suspect the (internal) protective circuitry guaranteeing the "5V tolerance" might be to blame for the large observed "parasitic" capacity.
Especially suspicious is that it almost exclusively affect the rise time. 

So, I nonetheless recommend to try pull-ups to 3.3V instead 5V.