I2C speed problems

[JonConesa]

Hi everyone,

I’m currently working on an I2C communication setup using the Nucleo-H753ZI DK but the cubeMx document is for the STM32H743BIT (the MCU for my custom board) and aiming to run it in Fast Mode (400 kHz). However, when configuring the I2C clock speed to 400 kHz, the CLK signal becomes unstable, as shown in the attached image.

To ensure the setup is functioning correctly, I ran tests with I2C configured at 100 kHz, and the communication works perfectly in that case.

I’ve also included an image of the system clock configuration in case there’s something that could be optimized.

Does anyone know what might be causing the instability in the CLK signal, preventing proper communication at 400 kHz?

Thanks in advance for your help!

[Ozone]

A 3.3k pull-up will be ok.

> I’m aiming for a 400 kHz CLK speed, but currently, I’m getting a 378 kHz waveform instead.

A 378 kHz waveform based upon what ?
If you use a scope and measure this via distance between cursors, there is an inherent inaccuracy involved.
Try a higher time scale resolution, perhaps averaging over several cycles.

And second, the peripheral clock (to the I2C) might be off a bit.

> To achieve that I had to reduce the resistor to 100 Ohm. 

If you talk about I2C pull-up resistors here, this is a bad idea.
Check the MCU datasheet for GPIO / I2C driver current limits.

[TDK]

A logic analyzer is perfectly fine here for a 400 kHz signal. The issue is the sampling rate on the logic analyzer (in addition to the weak pullups).

[Andrew Neil]

But the scope view would immediately & directly show the rise-time issue - which is not visible on a LA view.

[TDK]

While true, the rise time on all bits is the same, so any errors will be cancelled out and the displayed clock rate will be accurate to the precision of the sample rate. The duty cycle will not be representative, however that doesn't matter here.

(In this case, the logic analyzer in question can also do analog captures anyway, so this is all academic.)

[JonConesa]

Hi Padawan,

I am using an oscilloscope to measure the frequency, and the resistor reduction was made to achieve the correct waveform for the CLK signal.

For the pull-up, I am using 5V.

Attached are some measurements I have taken with different resistor values and VCC levels:

• 100 Ohms, 5V:

• 2k2, 5V:

• 1k, 3.3V:

Best regards,

Jon

[Andrew Neil]

So you're expecting the the I2C pins to sink 50 mA ?!

[JonConesa]

Hi Andrew,

I see that could be a problem but I must achieve 400kHz in the I2C. Regarding the maximum I2C current limits are 25 mA for the PCA. 

What would you recommend?

[TDK]

I2C is not a fixed speed. It must wait (per the I2C spec) until a specific voltage is reached during the rising clock cycle. Since your edges are slow, the final clock speed is lower than 400 kHz. You can see the speed increase as your pullups get stronger.

A clock speed of 370 kHz or lower does not pose a problem in terms of communication.

[Andrew Neil]

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@JonConesa wrote:

What would you recommend?

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You need to give more details of your setup.

It seems you have very high capacitance - why is that?

Maybe you need something better than just a simple pullup; eg,

https://www.nxp.com/docs/en/user-guide/UM10204.pdf#page=52

Bus "Accelerators" are available; eg,

https://www.analog.com/en/products/ltc1694.html

[Ozone]

There is something wrong here, these rise times are horrible.

I would suggest to post the relevant part of the schematics of your board here - i.e. everything that is connected to the pins used for I2C.

> For the pull-up, I am using 5V.

A very bad idea.
You must use 3.3V. If the I2c slave(s) are 5V, use level shifters.