2023-03-26 09:04 AM
tested on nucleo stm32h723 board with STM32CubeIDE (only main.c is modified)
What does this example?
Timer3 triggers an interrupt every 40 microseconds. The interrupt toggles PC8 for ~2ms. Additionally we trigger a FMC data transfer every second for 10 seconds.
What is the Problem?
Every second during the FMC data transfer our interrupt handler is somehow delayed!
The global variable "ticks_end_max" contains the maximum number of the timer3 counter register just before the interrupt ends. This max counter value is ~2600, but only ~600 if FMC access commented out!
Using an oscilloscope on pins PC8 and PC9 is also possible. PC9 is configured as TIM3_CH4 and emits a 4us low pulse each cycle. PC8 is toggled for ~2us during interrupt. Trigger on rising edge of PC8 when PC9 is low.
Solved! Go to Solution.
2023-04-04 10:03 AM
First of all much thanks to @Community member who was completely right!
Then I might to point out that the title of the thread is misleading. Not the interrupt itself is delayed. Only the first memory access which uses AXI is delayed.
We now simply execute a dummy read (which also uses the AXI) after every write to the very slow IC that is connected via FMC. This way we prevent the AXI buffer to get filled up with our very slow memory writes.
Although this is not an elegant solution, the measures overhead in our case is less than 1%.
Would be interesting to hear if someone has a better solution?
2023-04-05 12:41 AM
"Better" is heavily dependent on particular application's details here. For example, would the processor never access FMC (e.g. performing the FMC reads/writes exclusively through DMA), the processor's store buffer would not get clogged and GPIO write from processor would not get delayed. (Note that DMA would still clog the FMC row's buffer (probably 3-deep) in the AXI matrix, so if there are processor-originated accesses to FMC, even if to fast targets, the processor would need to wait until those accesses are fulfilled anyway).
It is most probably not be worth the hassle, though.
JW