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HRTIM on STM32G4 and STM32H7 "Update Interrupts" are not working when preload is disabled.

vchilapu
Associate II

In the STM32CubeMX there is a preload setting. If I enable the preload then I can see the update interrupts are working as expected. But, if the preload setting is set to disabled, then no update interrupts are seen. This is true for all timers A-F and also Master timer.

NOTE: Only the update interrupt is impacted here, while other interrupts are working fine.

1 ACCEPTED SOLUTION

Accepted Solutions
Vincent Onde
ST Employee

Hi @vchilapu​,

This behavior is normal: as the preload functionality is disabled, there's no register content update anymore (all write accesses are directly done in active registers). There are not update events and thus no interrupts.

Best regards,

Vincent

View solution in original post

3 REPLIES 3
Amel NASRI
ST Employee

Hi @vchilapu​,

@Vincent Onde​ provided an explanation for this behavior in this question: STM32G474 discovery kit HRTIM ISR (HRTIM1_TIMA_IRQHandler) not hit for channel set Interrupt(SETx1) and channel reset interrupt(RSTx1).

Do you confirm that this answers your question?

-Amel

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

Hi Amel,

Thank you for your quick response.

@Vincent Onde​ suggestion was when preload is enabled we have to ensure an update event is put in place such that interrupt flags are copied to the active register. But in this case, the preload option is disabled. So all the updates go to the active register directly. In this context, all interrupts should work even if any update events are not triggered. But, what I see is only the update interrupt is not working.

NOTE: Only the update interrupt is impacted here, while other interrupts are working fine.

Vincent Onde
ST Employee

Hi @vchilapu​,

This behavior is normal: as the preload functionality is disabled, there's no register content update anymore (all write accesses are directly done in active registers). There are not update events and thus no interrupts.

Best regards,

Vincent