ChipSelectHighTime limits seems to be wrong for STM32H72x/3x inside HAL OCTOSPI drivers

[hknief]

I'm operating an Infineon F-RAM CY15B116QSN at the OctoSPI port of an STM32H735 MCU with 100 MHz clock (F-RAM devices is specified up to 108MHz). The F-RAM datasheet requires a CS high time between commands of at least 145 ns, which requires 15 clock cycles @100MHz. 

The CubeMX tool limits the CS high time up to 8 cycles (3 bits wide); the same applies to the STM32H7xx HAL driver, which asserts, if this value is outside the range 1 to 8. In contrast to these limitations, the STM32H73x reference manual allows a CS high time of 1 to 64 (6 bits wide), which would suffer our needs !

Actually I added a copy of the 'HAL_OSPI_Init' function with different name to my project to get around this limitation, but it would be fine, if this bug will be fixed in future versions - or am I wrong at some point ?

Best regards, Heino

[KDJEM.1 · Accepted solution]

Hello @hknief  and welcome to the Community,

Thank you for bringing this issue to our attention.

I reported this issue internally.

Internal ticket number: 194557 (This is an internal tracking number and is not accessible or usable by customers).

Thank you.

Kaouthar