Tying SPI inputs together to run several ADCs at once

[Ajaho]

Dear Community,

I'm working on STM32H743ZIT6 based project.

Here I want to set up 4 ADCs which have SPI interface.

On developer's forum is said "If all ADCs will be sampled at the same point in time with the same settings, then the SCLK, CS, and SDI can be tied together".

Also there mentioned: "Make sure the digital interface is able to drive all of the ADCs at once".

Is STM32H743ZIT6 able to drive all of the ADCs at once?

According to electrical characteristics:

Digital high input voltage logic level - 0.7V x DVDD (min) / DVDD + 0.3V (max);

Digital low input voltage logic level - -0.3 (min) / 0.2 x DVDD (max).

DVDD = 3.3V

Thanks!

[Michal Dudka]

Of course it must be connected. SPIs instances are independent, all SPIs need clock to determine when to sample data.

[AScha.3]

As i wrote :

> connecting the spi clk from master spi.

You have to use wires to put the needed clk from master to all slaves (except you have internal connection as on SAI modules, can couple 2 internal ); how the slave should doing "shift/clock in" without clock ?

So put some wires just at the cpu from master clk (out) to the slave clk (3 x clk (in)) .

[Ajaho]

Maybe here is some confusion.

According to ADC developer: "If all ADS8685 ADCs will be sampled at the same point in time with the same settings, then the SCLK, CS, and SDI can be tied together".

I tied together this input (for ADC) tracks and connected bunches to one (master) SPI.

This gives intentional purpose to send input signals from MCU to all ADCs at once.

When I set "Receive only slave" for 3 SPI, CubeIDE marked 2 pins as active: SDO and SCK.

But ADC SCK pins are already tied to one track and this is ok according to ADC dev..

[Michal Dudka · Accepted solution]

You need to route:
SCK from first SPI master to all ADCs and all SPI slaves
MOSI from first SPI master to all ADCs SDI
SDO from ADC1 to MISO of SPI master 
SDO from ADC2 to MOSI of first SPI slave 
SDO from ADC3 to MOSI of second SPI slave
SDO from ADC4 to MOSI of third SPI slave
CS from STM32 to all ADCs

[Michal Dudka]

By the way, why do you want to tie SCK + SDI together ? Your original solution with 4x separated ADC and SPI takes four times (SCK+SDI+SDO) + one CS. Completly 13 GPIOs. And "combined" solution takes SCK+MOSI+MISO (from master SPI) + four times (SCK+MOSI) + one CS. Completly 12 GPIOs. Why so much effort to save one pin on MCU ? Or it is due simpler and faster ADC reconfiguration ?

Sampling time of ADC is controlled by CS and that can be controlled by single pin in both cases.

[Michal Dudka]

Edit: 13 GPIOs versus 10 GPIOs 

[Ajaho]

Initially there were 4X4 pins used, now - 4 + 2X3.

But after your calcs I am not sure that did all right 🙂

[Michal Dudka]

A) fully independent variant has 4x(CS+SCK+MISO+MOSI)=16 and in that configuration you have full independent control over sampling/conversion time of each ADC and over their configurations.

B) Simply by conecting all CS to one MCU pin you have 1xCS+4x(SCK+MISO+MOSI)=16. Then sampling/conversion time is one for all ADC, but you are still able to configure each of them individualy (range, etc.).

C) Conecting also SCK and SDI together you get 1xCS+4xSCK+1xMOSI+4xSDI=10. Sampling/conversion time is one for all ADCs, and also configuration is common for all ADCs (all of them will have same range, etc.).

D) Connecting ADC in daisy chain you can reduce number of GPIO to 4. Sampling/conversion time is still common for all ADCs. Configuration is independent. Reading message is 4xtimes logner then in previous cases.

[Ajaho]

Tanx for the your massive advice!

My variant is C)