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SysTick on STM32G0

DRobe.4
Senior

I am trying to use SysTick on STM32G070. Clock tree must be OK because everything else works, as far as I can tell, but when I include the following code (Keil compiler does not flag errors or warnings), in my initialization routine, interrupts stop. I don't want SysTick to generate interrupts, I just want SysTick to run at SYSCLK/8 =  64 MHz/8 = 8 MHz.

// Initialize SysTick
SysTick->LOAD = 0xFFFFFF; // After counting down to 0, next value is 0xFFFFFF
SysTick->VAL = 0;
SysTick->CTRL = 0x01; // Enabled, clocked at 8 MHz, no interrupt

5 REPLIES 5
DRobe.4
Senior

I think I found the answer. My code uses HAL_Delay() which probably uses the SysTick interrupt, which I disabled in the snippet in my original post. As everyone is aware, calls to HALxxxx are everywhere in STM32 code, so other mysterious failure may arises, even though I will explicitly stop using HAL_Delay(). Who knows were SysTick is used in the HAL universe.

TDK
Guru

HAL_Delay requires SysTick in order to function. A lot of HAL functions call HAL_Delay.

You can re-define HAL_Delay and similar function to use something else if you want since they are weakly defined. I have them all using DWT->CYCCNT instead in order to eliminate systick interrupts entirely while keeping the same functionality. Unsure if the G0 has DWT, but if not, it has other timers.

If you feel a post has answered your question, please click "Accept as Solution".

How can I find out which HAL functions use SysTick, so that I can avoid them? SysTick amongst all the G0 timers, is 24 bit, allowing me to time events down to 1/8 usec over a complete 1 second loop time. And while I am complaining, I wish Arm had the 64 bit counter included in RISC-V and that counter even has the ability to set an interrupt at any 64 bit count, not just at underflow 0.

You can open up the HAL files and look at them.

If you feel a post has answered your question, please click "Accept as Solution".

I wish Arm had the 64 bit counter included in RISC-V

ARM has nothing to do with RISC-V.